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This appendix defines the key terms and concepts that you should understand to use the Timing Analyzer effectively. The terms are listed in alphabetical order.
A Basic ELement. Basic Elements are the building blocks that make up a CLB, IOB, BLOCK RAM, or TBUF - function generators, flip-flops, carry logic, and RAMs.
The CLB (Configurable Logic Block) constitutes the basic FPGA cell. The FPGA is an array of CLBs organized in columns and rows on the silicon die. CLBs are used to implement macros and other designed functions. They provide the physical support for an implemented and downloaded design. They have inputs on each side, and this versatility makes them flexible for the mapping and partitioning of logic. See The Programmable Logic Data Book for each device's CLB.
A clock input path is a logic transition, which when applied to a clock pin on a synchronous element, captures data. It starts at either an input or an output of the chip, but can also start at other sequential elements. A clock input path propagates through any number of levels of combinatorial logic and ends at any clock pin on a flip-flip, latch, or synchronous RAM. These paths do not propagate through synchronous elements. The clock input path time is the maximum time required for the signal to arrive at the clock input of the synchronous element.
The difference between the time a clock signal arrives at the source flip-flop in a path and the time it arrives at the destination flip-flop.
A path starting at the Q output of a flip-flop or latch and ending at an output of the chip. It includes the clock-to-Q delay of the flip-flop and the path delay from that flip-flop to the chip output. The clock-to-pad path time is the maximum time required for the data to leave the source flip-flop, travel through logic and routing, and arrive at the output.
A path starting at the Q output of a flip-flop or latch and ending at an input to another flip-flop, latch, or RAM, where that pin has a setup requirement before a clocking signal. It includes the clock-to-Q delay of the source flip-flop, the path delay from that flip-flop to the destination flip-flop, and the setup requirement of the destination flip-flop. The clock-to-setup path time is the maximum time required for the data to propagate through the source flip-flop, travel through the logic and routing, and arrive at the destination before the next clock edge occurs.
A logical configuration that will, at some point, go into a physical site. Examples of components are CLBs, IOBs, tristate buffers, pull-up resistors, and oscillators.
Record of the commands that you invoked during a session.
The path within a design that dictates the fastest time at which an entire design can run. This path runs from the source to a sink node such that if any activity on the path is delayed by an amount t, then the entire circuit function is delayed by time t.
A sink node or stopping point for a timing analysis path, often the data input of a synchronous element or a pad.
A node which acts as either the driver to begin a path or a load to end a path.
A set of limitations or options applied to the timing analysis to more specifically target important items of interest.
The process of putting logic from your design into physical macrocell locations in a CPLD. Routing is performed automatically, and because of the interconnect architecture, all designs are routable.
A group of macrocells in a CPLD that can efficiently perform complex logic such as arithmetic operations.
The time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.
A collection or grouping of basic elements that implement the input and output functions of FPGA and CPLD devices.
A physical macro is a logical function which has been mapped into the components of a specific device family. Physical macros are stored in files with the extension .nmc. In addition to components and nets, the file can also contain placement, routing, or both kinds of information. A macro can be unplaced, partially placed, or fully placed. It can also be unrouted, partially routed, or fully routed. See the “Working with Physical Macros” chapter of the FPGA Editor Guide for information about physical macros.
Specific to the Timing Analyzer, a macro is an ASCII file containing a sequence of Timing Analyzer keyboard commands that are executed in script form.
The background against which windows are displayed.
The area located at the top of the main window that provides access to the menus.
A logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.
Defines the timing relationship between an external clock and its associated data-in or data-out pin.
The physical bonding pad on an Integrated Circuit. All signals on a chip must enter and leave by way of a pad. Pads are connected to package pins in order for signals to enter or leave an Integrated Circuit package.
A path starting at an input of the chip and ending at an output of the chip. The pad-to-pad path time is the maximum time required for the data to enter the chip, travel through logic and routing, and leave the chip. It is not controlled or affected by any clock signal.
A path starting at an input of the chip and ending at an input to a flip-flop, latch, or RAM - wherever there is a setup time against a control signal. The pad-to-setup path time is the maximum time required for the data to enter the chip, travel through logic and routing, and arrive at the input before the clock or control signal arrives.
An ordered set of elements identifying a logic flow pathway through a circuit. A path may consist of a single net or a grouping of related nets and components. There can be multiple paths (consisting of nets and components) between the two pins. When a component is selected as part of a path, both the input pin to the component and the output pin are included in the path. A path stops when it reaches the data input of a synchronous element (flip-flop) or pad. A path usually starts at the output of a synchronous element or pad.
Paths can be defined by using timing specifications. See the “Using Timing Constraints” chapter of the Development System Reference Guide. In the “Path Example” figure, there are three paths between Pin A and Pin B. One path travels from Pin A through LB2 and through LB6 to Pin B, another travels from Pin A through LB3 and through LB6 to Pin B, and another travels from Pin A through LB4, LB5, and LB6 to Pin B.
Figure A.1 Path ExampleThe time specified for a clock signal to transition from a state back to the same state. Also, a requirement placed on the clock signal that the place and route software is expected to meet. The period of the clock is affected by the amount of time it takes the output of one sequential element to pass to the next sequential element in a path.
A symbol pin or package pin. A package pin is a physical connector on an Integrated Circuit package that carries signals into and out of an Integrated Circuit.
A symbol pin, also referred to as an instance pin, is the connection point of an instance to a net.
A logic element that directly corresponds, or maps, to a basic element.
A hierarchical diagram representing a design in terms of user and library components.
Standard Delay Format, which is an industry-standard file format for specifying timing information. It is often used for simulation.
A flip-flop, synchronous RAM, or Latch.
The time relative to a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct.
The difference between the constraint and the analyzed value, with negative slack indicating an error condition.
An output pin that drives a path. Sources are input pads and the outputs of synchronous elements.
A point-to-point delay analysis of a design network with respect to a given set of constraints. It does not include insertion of stimulus vectors.
An area located at the bottom of an application window that provides information about the commands that you are about to select or that are being processed.
A collection of design elements, including nets, BELs, components, and so forth that can be used to constrain many objects in the same way.
A series of constraints applied to a given set of paths or nets that dictate the desired performance of a design. Constraints may be period, frequency, net skew, maximum delay between end points, or maximum net delay.
A group of buttons with graphic icons located under the menu bar in the application window that provide button access to frequently used commands in pull-down menus.
The Timing Reporter And Circuit Evaluator provides static timing analysis of a design based on input timing constraints. Its two major functions are timing verification and reporting.
The routing matrix for CPLD devices. This fully populated switching matrix allows any output to be routed to any input, guaranteeing
100 percent routability of all designs. The UIM can also function as a very wide AND gate, which can allow more logic to be placed in macrocells.
In timing, the process of comparing the desired performance of a design using constraints against the expected performance, based on software models of the device speed and routing delays.
An acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High-Speed Integrated Circuits) or HDL, which can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level.