Inputs and Outputs

The Timing Analyzer has the following input and output capabilities:

• Accepts NCD design files and physical constraints files (PCF) output by the mapper for FPGAs
  
  
• Accepts VM6 (CPLD) design files output by the fitting software
  
  
• Loads macro files (XTM) as input
  
  
• Creates timing report (TWR) files as output
  
  
• Creates macro (XTM) files
  
  

  Note: When you load a design, the Timing Analyzer also loads the default PCF file if it is present. The default PCF file is the physical constraints file with the same name and located in the same directory as the NCD file. You can load a different PCF file after the design is loaded. The order of the timing constraints in the PCF file is reflected in the Timing Analyzer reports. CPLD physical constraints information is contained in the VM6 file itself.