|
|
|
|
|
| Command | Syntax | Description |
|---|---|---|
| AnalyzeAdvancedDesign | aad [save file_name.twr] | Generates report indicating overall design performance |
| AnalyzeCustom | ac [save file_name.twr] | Generates report containing worst-case path delays for paths in design, except those suppressed by filtering commands |
| AnalyzeTimingConstraints | atc [save file_name.twr] | Generates report indicating whether design meets timing constraints |
| ControlPathTracing | cpt {Enable|Disable} {reg_sr_q | lat_d_q | ram_d_o | ram_we_o | tbuf_t_o | tbuf_i_o | io_pad_i | io_t_pad | io_o_i | io_o_pad | io_t_i} component_name... | Controls path tracing through components |
| DefineEndPoints | dep {fall | tall} dep {fpad|tpad} pad_name dep {fclb|tclb} CLB_name dep {fnet|tnet} net_name dep {fpin|tpin} pin_name dep {fff|tff} flip-flop_name dep {fee|tee} clock_name dep {fris|tris} clock_name dep {fmc|tmc} macrocell_name dep {ffal|tfal} clock_name dep {fram|tram} RAM_name dep {fl|tl} latch_name dep {ftg|ttg} timegroup_name | Defines path starting and ending points |
| DelayGreaterThan | dg delay_value | Specifies minimum delay. Only supports analysis of CPLD designs |
| DelayLessThan | dl delay_value | Specifies maximum delay. Optional CPLD-only command |
| DoHoldRaceCheck | dhrc {true | false} | Do hold/race checking when analyzing the design |
| DropTimingConstraint | dtc [time_constraint1 time_constraint2 ...] | Omits specified timing constraints from analysis |
| ExcludeNets | exnet [net_name1 net_name2 ...] | Prohibits analysis of specified nets |
| Exit | exit | Exits the Timing Analyzer |
| IncludeNets | incnet [net_name1 net_name2 ...] | Limits analysis to paths containing specified nets |
| IncludeNoTimingConstraint | intc {true | false} | Forces reporting of paths with no timing constraints |
| MaxPathsPerTimingConstraint | mpptc number_of_paths | Limits the total number of paths reported per timing constraint |
| OmitUserConstraints | ouc {true | false} | Enables or disables user-specified constraints in the PCF file |
| OnlyLongestPaths | olp {true | false} | Reports only path with longest delay for each constraint. Only supports analysis of CPLD designs |
| OpenDesign | od {design_name.ncd | design_name.vm6} | Loads a design for timing analysis |
| OpenPCF | op file_name.pcf | Opens an existing physical constraints file |
| ProratingOptions | po {T {degrees_celsius}} {V {voltage}} | Controls temperature and voltage prorating |
| Query | qy {Net | TimeGroup} element_name | Displays timing information about groups of elements |
| Report | r {wide | normal} | Determines format of reports |
| ResetAllPathFilters | rapf | Causes path filters to revert to default |
| RunMacro | runm file_name.xtm | Runs macro |
| SelectFailingTiming-Constraint | sftc {true | false} | Limits reporting to paths that do not meet timing constraints |
| SetForce | sf {on | off} | Suppresses messages when macro is run |
| ShowClockNets | scn [save file_name] | Show or hide the window showing the clock nets |
| ShowSettings | ss [save file_name] | Show or hide the window displaying current settings of filters and command option settings |
| SortOn | sort {Ascend | Descend | SourceNet | DestNet | SourceClkNet | DestClkNet} | Specifies how paths are sorted when they are reported. Only supports analysis of CPLD designs |
| Speed | sp speed_grade | Changes speed grade during analysis |