ControlPathTracing

The ControlPathTracing command controls path tracing through RAMs, tristate buffers, input and output pins, components, and Set/Reset logic. These paths may be irrelevant to your analysis.

Note: This command only applies to FPGAs; it does not function if a CPLD design is open. (CPLD path timing analysis ignores paths through Set/Reset logic and breaks paths at bidirectional I/O pins.)

This command is equivalent to the Path Filters Common Filters Control Path Tracing menu command.

Syntax

The syntax of the ControlPathTracing command is the following.

ControlPathTracing {Enable|Disable} {reg_sr_q|lat_d_q|ram_d_o|ram_we_o|tbuf_t_o|tbuf_i_o|io_pad_i|io_t_pad|io_o_i|io_o_pad} component_name component_name...

• reg_sr_q enables path tracing through CLB flip-flop asynchronous Set or Reset outputs. By default, this path is disabled; the Timing Analyzer does not analyze these paths.
  
  
• lat_d_q enables path tracing from the latch D input to the Q output. By default, this path is disabled; the Timing Analyzer does not analyze these paths.
  
  
• ram_d_o enables path tracing through the data inputs of a CLB RAM. By default, this path is disabled; the Timing Analyzer does not analyze these paths.
  
  
• ram_we_o disables path tracing through the write-enable input of a CLB RAM. By default, this path is enabled; the Timing Analyzer analyzes these paths.
  
  
• tbuf_t_o disables path tracing of paths that pass through a T pin to the O pin. By default, this path is enabled; the Timing Analyzer analyzes these paths.
  
  
• tbuf_i_o disables path tracing from the input pin to the output pin of a TBUF. By default, this path tracing is enabled; the Timing Analyzer analyzes these paths.
  
  
• io_pad_i disables path tracing from the pad pin to the input pin of an IOB. By default, this path tracing is enabled; the Timing Analyzer analyzes these paths.
  
  
• io_t_pad disables path tracing from the tristate control pin of an IOB to the pad, or if the architecture supports it, the path through the data input to output of the tri-state enable latch. By default, this path tracing is enabled; the Timing Analyzer analyzes these paths.
  
  
• io_o_i disables path tracing of paths from the IOB O pin to the I pin. By default, this path is enabled but is disabled for tristate IOBs; the Timing Analyzer analyzes these paths.
  
  
• io_o_pad disables path tracing from the output pin of an IOB to the pad pin. By default, this path tracing is enabled; the Timing Analyzer analyzes these paths.
  
  
• Component_name is the name(s) of the CLBs, IOBs, or TBUFs that the path goes through.
  
  

Abbreviation

Abbreviate the ControlPathTracing command syntax as follows.

cpt {Enable|Disable} {reg_sr_q|lat_d_q|ram_d_o|ram_we_o|tbuf_t_o|tbuf_i_o|io_pad_i|io_t_pad|io_o_i|io_o_pad} component_name component_name...

Example

Following is an example of the ControlPathTracing command.

controlpathtracing ram_we_o CLB_R4C4