Foundation Series 2.1i User Guide

About This Manual

This Foundation Series 2.1i User Guide provides a detailed description of the Foundation™ design methodologies, design entry tools, simulation (both functional and timing simulation). Information on synthesis is included for Foundation Express users.The manual also briefly describes the Xilinx design implementation tools. Detailed descriptions of the design implementation tools can be found in two other online books, Design Manager/Flow Engine Guide and Development System Reference Guide.

Before using this manual, you should be familiar with the operations that are common to all Xilinx software tools: how to bring up the system, select a tool for use, specify operations, and manage design data. These topics are covered in the Foundation Series 2.1i Quick Start Guide. Consult the Verilog Reference Guide and the VHDL Reference Guide for detailed information on using Verilog and VHDL with Foundation Express.

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this page. You can also directly access some of these resources using the provided URLs.

Resource	Description/URL
Tutorial	Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm
Answers Database	Current listing of solution records for the Xilinx software tools Search this database using the search function at http://support.xilinx.com/support/searchtd.htm
Application Notes	Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm
Data Book	Pages from The Programmable Logic Data Book, which describe device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm
Xcell Journals	Quarterly journals for Xilinx programmable logic users http://support.xilinx.com/xcell/xcell.htm
Tech Tips	Latest news, design tips, and patch information on the Xilinx design environment http://support.xilinx.com/support/techsup/journals/index.htm

Manual Contents

This guide covers the following topics:

Chapter 1, “Introduction,” lists supported architectures, platforms, and features. It also lists the available documentation and tutorials to help you get started with Foundation.
Chapter 2, “Project Toolset,” explains the two Foundation project types - Schematic Flow projects and HDL Flow projects - and how to access the various Foundation design tools from the Project Manager. It briefly describes each tool and its function.
Chapter 3, “Design Methodologies - Schematic Flow,” describes various design methodologies for top-level schematic designs and state machine designs in Schematic Flow projects.
Chapter 4, “Schematic Design Entry,” explains how to manage your schematic designs and how to create hierarchical schematic designs.
Chapter 5, “Design Methodologies - HDL Flow,” describes various design methodologies for HDL, schematic, and state machine designs in HDL Flow projects.
Chapter 6, “HDL Design Entry and Synthesis,” describes how to create top-level HDL designs, explains how to manage large designs, and discusses advanced design techniques.
Chapter 7, “State Machine Designs,” explains the basic operations for creating state machine designs.
Chapter 8, “LogiBLOX,” explains how to create LogiBLOX^™ modules and how to use them in schematic and HDL designs.
Chapter 9, “CORE Generator System” gives an overview of the Xilinx CORE Generator System.
Chapter 10, “Functional Simulation,” describes the basic functional simulation process.
Chapter 11, “Design Implementation,” briefly describes how to implement your design with the Xilinx Implementation Tools. The chapter also describes how to select various design options in the Implementation Options dialog box and describes the Implementation reports.
Chapter 12, “Verification and Programming,” explains how to generate a timing-annotated netlist, how to perform a static timing analysis, and describes the basic timing simulation process. An overview of the device download tools is also included.
Appendix A, “Glossary,” defines some of the commonly used terms in this manual.
Appendix B, “Foundation Constraints,” discusses some of the more common constraints you can apply to your design to control the timing and layout of a Xilinx FPGA or CPLD. It describes how to use constraints at each stage of design processing.
Appendix C, “Instantiated Components,” lists the components most frequently instantiated in synthesis designs.
Appendix D, “File Processing Overview,” contains diagrams of the file manipulations for FPGAs and CPLDs during the design process.

Conventions

This manual uses the following typographical and online document conventions. An example illustrates each typographical convention.

Typographical

The following conventions are used for all documents.

Courier font indicates messages, prompts, and program files that the system displays.

speed grade: -100
Courier bold indicates literal commands that you enter in a syntactical statement. However, braces “{ }” in Courier bold are not literal and square brackets “[ ]” in Courier bold are literal only in the case of bus specifications, such as bus [7:0].

rpt_del_net=

Courier bold also indicates commands that you select from a menu.

File Open
Italic font denotes the following items.
- Variables in a syntax statement for which you must supply values
  
  edif2ngd design_name
- References to other manuals
  
  See the Development System Reference Guide for more information.
- Emphasis in text
  
  If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required.

edif2ngd [option_name] design_name
Braces “{ }” enclose a list of items from which you must choose one or more.

lowpwr ={on|off}
A vertical bar “|” separates items in a list of choices.

lowpwr ={on|off}
A vertical ellipsis indicates repetitive material that has been omitted.

IOB #1: Name = QOUT' IOB #2: Name = CLKIN' . . .
A horizontal ellipsis “. . .” indicates that an item can be repeated one or more times.

allow block block_name loc1 loc2 ... locn;

Online Document

The following conventions are used for online documents.

Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click the red-underlined text to open the specified cross-reference.
Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click the blue-underlined text to open the specified cross-reference.