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Once you have completed design entry and are ready for physical implementation of the design, you begin implementation processing by clicking the Implementation button on the project flowchart. All the steps needed to obtain the final results are invoked automatically. Refer to the “Design Implementation” chapter for more information.
You can control the implementation of your design with a user constraints file, an implementation guide file, or a Floorplanner file. You can set these files by selecting Implementation 
Set Guide File(s), or Set Floorplan File(s), or Set Constraints File(s) from the Project Manager. Or, you can access a dialog box to set the files by clicking the Control Files SET button in the Physical Implementation Settings section of the window that appears when you implement a new version or revision of your design.
Constraints can be applied to control the implementation of a design. Location constraints, for example, can be used to control the mapping and positioning of logic elements in the target device. Timing constraints can be used to identify critical paths that need closer placement and faster routing. For a list of the constraints that can be applied for the various devices, refer to the “Attributes, Constraints, and Carry Logic” chapter of the Libraries Guide.
The User Constraints File (UCF) is a user-created ASCII file that holds the constraints. You can enter the constraints directly in the input design. However, putting them in the UCF separates them from the input design files and provides for easier modification and reduces re-synthesis of your design. You can create the UCF using a text editor or you can use the Xilinx Constraints Editor to produce the UCF for you. UCF files can also be reused from design to design.
Guide files from a previous implementation can be used to speed up the current implementation. When an implementation guide file is specified, only the sections of the current revision that are different from the specified guide file for the previous revision are processed.
The Floorplanner tool generates an MFP file that contains mapping and placement information. You can use this file as a guide for mapping an implementation revision for the XC4000, Spartan, and Virtex device families only. For Floorplanner guide files information, refer to the Floorplanner Guide, an online manual.
Typically, designs are implemented by using the Implementation button on the project flowchart. However, you can access certain specialized functions from the Project Manager Tools menu.
The Constraints Editor accessed from the Project Manager by selecting Tools Implementation Constraints Editor is the Xilinx Constraints Editor. It becomes available for design implementation after the translation step in Flow Engine has completed. For more on the Constraints Editor, refer to the Constraints Editor Guide, an online book.
The Flow Engine processes the design, controls the implementation of the design, and guides the implementation revisions. When initiated by selecting Tools Implementation Flow Engine, the Flow Engine is run as a standalone program. The project is not automatically brought up-to-date as it is when initiated by the Implementation button on the project flowchart. For more information, see the “Implementing a Design” section of the “Design Implementation” chapter.
Selecting Tools Implementation Floor Planner from the Project Manager window, accesses the Floorplanner tool (for FPGAs only).The Floorplanner creates a file that contains mapping information, which can be used by the Flow Engine as a guide for mapping an FPGA implementation revision. For more information on the Floorplanner, see the Floorplanner Guide, an online book.
Selecting Tools Implementation FPGA Editor from the Project Manager window opens the FPGA Editor. The FPGA Editor provides a graphic view of your placed and routed design, allowing you to make modifications. This option is supported for FPGAs only.
For more information on using the FPGA Editor, see the FPGA Editor Guide, an online book.
Selecting Tools Implementation CPLD ChipViewer from the Project Manager window opens the ChipViewer. The ChipViewer provides a graphical view of the CPLD fitting report. With this tool you can examine inputs and outputs, macrocell details, equations, and pin assignments. You can examine both pre-fitting and post-fitting results.
More information on using the CPLD ChipViewer is available in that tool's online help or from the Umbrella Help menu accessed by Help Foundation Help Contents Advanced Tools ChipViewer.
I/O pins can be locked to a previous revision by clicking on the revision in the Versions tab of the Project Manger and selecting Tools Implementation Lock Device Pins. The Lock Pins Status dialog appears upon completion. You can click View Lock Pins Report from the Lock Pin Status dialog or select Tools Implementation View Locked Pins Report to access the Lock Pins Report. The Lock Pins Report contains information on any constraint conflicts between the pin locking constraints in the existing UCF file and the design file.