Design Methodology

The following figure shows a typical design process that uses Foundation Express and a VHDL simulator.

Figure 1.2 Design Flow

The numbers in the above figure are explained below.

1. Write a design description in VHDL.
   
   This description can be a combination of structural and functional elements (as shown in the “Design Descriptions” chapter). Both Foundation Express and a VHDL simulator use this design description.
   
   
2. Provide VHDL test drivers for the simulator.
   
   The drivers supply test vectors for simulation and gather output data. To learn about writing these drivers, see the appropriate simulator manual.
   
   
3. Simulate the design by using a VHDL simulator and verify that the description is correct.
   
   
4. Using Foundation Express, synthesize and optimize the VHDL design descriptions into a gate-level netlist.
   
   Foundation Express generates optimized netlists to satisfy timing constraints for a targeted FPGA architecture.
   
   
5. Using your Foundation development system, link the FPGA technology-specific version of the design to the VHDL simulator.
   
   The development system includes simulation models and interfaces required for the design flow.
   
   
6. Simulate the technology-specific version of the design with the VHDL simulator.
   
   You can use the original VHDL simulation drivers from Step 2, because module and port definitions are preserved through the translation and optimization processes.
   
   
7. Compare the output of the gate-level simulation (Step 6) against the output of the original VHDL description simulation (Step 3) to verify that the implementation is correct.