Direct Instantiation

A component instantiation statement

• Defines a subcomponent of the design entity in which it appears
  
  
• Associates signals or values with the ports of that subcomponent
  
  
• Associates values with generics of that subcomponent
  
  

The following two examples show the difference between a component instantiation statement and the more concise direct component instantiation statement.

ARCHITECTURE struct OF root IS

   COMPONENT leaf

      PORT (

         clk,data : in std_logic;

         Qout : out std_logic);

   END COMPONENT;

BEGIN

   u1 : leaf

      PORT MAP (

         clk => clk,

         data => d_in(0),

         Qout => q_out(0));

The following example shows how you can express the information in the previous example in a direct component instantiation statement.

ARCHITECTURE struct OF root IS

BEGIN

   u1 : entity work.leaf(rtl)

      port map (

         clk => clk,

         data => d_in(0),

         Qout => q_out(0));