PPT 슬라이드
type std_logic is ( ‘U’ ; -- Uninitialized ‘X’ ; -- Forcing Unknown ‘0’ ; -- Forcing Zero ‘1’ ; -- Forcing One ‘Z’ ; -- High Impedance ‘W’ ; -- Weak Unknown ‘L’ ; -- Weak Zero ‘H’ ; -- Weak One ‘ - ‘; -- Don’t Care )
Type Std_logic was developed from the MVL (Multi-Value Logic) system and provides for more detailed hardware modeling. It supports different signal strengths, “don't-care” conditions and bussed structures with tri-state drivers. (Defined in package std_logic_1164)
Note: type bit is limited to (‘0’, ‘1’).