PPT 슬라이드
- 2 to 1 Mux (Gate Combination)
library ieee;
use ieee.std_logic_1164.all;
entity mux2 is
port (
i0,i1 : in std_logic;
sel : in std_logic;
y : out std_logic
);
end mux2;
architecture gate_mux2 of mux2 is
begin
y <= (i0 and (not sel)) or (i1 and sel);
end gate_mux2;