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- 4 to 1 Mux (WITH SELECT WHEN±¸¹®)
library ieee;
use ieee.std_logic_1164.all;
entity mux4 is
port (
i0,i1,i2,i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
y : out std_logic
);
end mux4;
architecture behave_mux4 of mux4 is
begin
with sel select
y <= i0 when ¡°00¡±,
i1 when ¡°01¡±,
i2 when ¡°10¡±,
i3 when ¡°11¡±,
¡®0¡¯ when others;
end behave_mux4;