PPT 슬라이드
- Compare Two Variable Input
library ieee;
use ieee.std_logic_1164.all;
entity comp is
port (
a,b : in std_logic_vector(3 downto 0);
eq,agb,alb : out std_logic
);
end comp;
architecture a_comp of comp is
begin
eq <= ‘1’ when a = b else ‘0’;
agb <= ‘1’ when a > b else ‘0’;
alb <= ‘1’ when a < b else ‘0’;
end a_comp;