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Counter ±¸¹®(3)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt8e is
port (
rst,en : in std_logic;
clk : in std_logic;
q : out std_logic_vector(7 downto 0)
);
end cnt8e ;
architecture Behave of cnt8e is
signal tq : std_logic_vector(7 downto 0);
begin process (clk,rst)
begin
if rst = ¡®1¡¯ then
tq <= (others =>¡®0¡¯) ;
elsif ( clk¡¯event and clk = ¡®1¡¯ ) then
if en = ¡®1¡¯ then
tq <= tq + 1;
end if ;
end if ;
q <= tq;
end process;
end Behave;
Clk
Rst
Q
8
Counter with Enable
Cnt8E
EN
11
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