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Counter ±¸¹®(5)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt8sre is
port (
rst,en : in std_logic;
clk,sr : in std_logic;
q : out std_logic_vector(7 downto 0)
);
end cnt8sre ;
architecture Behave of cnt8sre is
signal tq : std_logic_vector(7 downto 0);
begin
process (clk,rst)
begin
if rst = ¡®1¡¯ then
tq <= (others =>¡®0¡¯) ;
elsif ( clk¡¯event and clk = ¡®1¡¯ ) then
if sr = ¡®1¡¯ then
tq <= (others =>¡®0¡¯) ;
elsif en = ¡®1¡¯ then
tq <= tq + 1;
end if ;
end if ;
q <= tq;
end process;
end Behave;
Clk
Rst
Q
8
Counter with Enable
and Sync Reset
cnt8sre
SR
EN
13
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