PPT ½½¶óÀ̵å
S to P Shift Register ±¸¹®
- Serial in Parallel Out Shift Register
use ieee.std_logic_1164.all;
q : out std_logic_vector(7 downto 0)
architecture Behave of s2p8 is
signal tq : std_logic_vector(7 downto 0)
elsif (clk¡¯event and clk = ¡®1¡¯) then