PPT 슬라이드

1.System Define

2. Algorithm Define

3. Architecture Define

4. VHDL Code Design

5. Function Simulation

6. Synthesis

7. Timing Simulation 1

8. Place & Route

9. Timing Simulation 2

10. Target Device 제조

11. Hard Ware Test

12. Mass Production

Design Flow

6. Synthesis

- Target Technology Library, Constraint

7. Timing Simulation 1

- Synthesis 결과로 Cell Delay가 반영된 Simulation.

8. Place & Route

- Target Device에 맞추기 위한(Timing, Size) Cell배치, 배선.

9. Timing Simulation 2

- Cell + Routing Delay가 포함된 Simulation.

10. Target Device 제조

- ASIC : Gate Array, Standard Cell, Full Custom (Test Vector,NRE)

- PLD : FPGA, PLD (Programming)

11. Hard Ware Test (On Board, Test Logic)

12. Mass Production

Design Flow (2)

10

이전 슬라이드

다음 슬라이드

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