With Xilinx design tools, you can translate Synopsys synthesized gate-level netlists for use with Cadence's Verilog-XL simulator. See the “Synopsys/Verilog Design Flow” figure.
NGDBuild accepts two types of Synopsys netlists, SXNF and SEDIF. Synopsys FPGA Compiler generates the SXNF netlist and Synopsys Design Compiler generates the SEDIF netlist. After you create one of the Synopsys netlists from a behavioral design, NGDBuild can translate the netlist into an NGD file or NGA file for use with the NGD2VER command. This command with its options generates the required files to run Verilog-XL simulation.
Figure D.1 Synopsys/Verilog Design Flow |  |
