Specifying Xilinx Properties and Constraints in Concept

This section describes various rules and restrictions for using Xilinx properties and constraints within Concept. This section also explains where you can obtain detailed information about how to add properties in Concept.

NOTE

This document uses the terms “properties” and “attributes” interchangeably.

Adding Xilinx Properties

For information about how to add properties within Concept, refer to the section “Using Properties” in Chapter 3, Creating a Design in the Cadence document, Concept Schematic User Guide.

A brief description of how to add a property to a component in Concept follows.

1. Within Concept, click on the Attribute button on the left-hand side of the editor window.
   
   
   
   

   Figure 3.2 Attributes Form

2. Click on the object to which you want to add a property.
   
   
3. When the Attribute Form displays, click the Add button in the lower right hand corner.
   
   
4. Scroll down to the bottom of the attribute list and enter the Name and Value in the new fields.
   
   

   ---

   NOTE

   Always enter properties as NAME-VALUE pairs.

   ---

   The buttons in the third column of the Attribute Form indicate what displays in the schematic window - the property NAME only, VALUE only, or BOTH. The default is set to VAL; only the value of the property displays on the schematic. For clarity, display both the NAME and the VALUE of the property.
   
   
5. Click Done when you finish adding properties.
   
   

Rules and Restrictions For Using Xilinx Properties in Concept

The following subsections describe rules, limitations, and restrictions for using Xilinx properties.

SIZE Property

The SIZE property is not supported and the Xilinx removed the property from all the components in the libraries. When placing an array of bodies, you must use Iterated Instances instead.

To use iterated instances, you must either add the PATH property to a new body, or edit the existing PATH property on a body already saved to the design.

PATH=body_name(n:m)

body_name is the name of the body you want to replicate, and (n:m) represents the range of indices over which you want to replicate the symbol. For example, if n=3 and m=0, you are replicating the body four times (0 through 3).

For high-level functional modules, including registers, counters, adders, and memory, you can also use the LogiBLOX utility.

See the “Understanding Iterated Instances” section in the “Schematic Guidelines” chapter in the Cadence manual, HDL Direct User Guide for more information.

CONCEPT2XIL Property Filter File

If you entered a Xilinx property on a schematic but did not list it in the property filter file ($XILINX/cadence/data/xilinx.pff), the EDIF file does not include the property after CONCEPT2XIL translation. The xilinx.pff file resides in $XILINX/cadence/data.

The xilinx.pff property filter file also contains entries for the predefined TIMESPECS TS01 through TS10 and the predefined TIMEGRPS GRP01 through GRP10. If you need additional TSidentifier or TIMEGRP properties, you must add them to the property filter file.

To customize your own xilinx.pff file, perform the following steps.

1. Copy the xilinx.pff file from $XILINX/cadence/data to your design directory.
   
   cp $XILINX/cadence/data/xilinx.pff your_design_directory
   
   

   ---

   NOTE

   Place the xilinx.pff file that you want to use in the directory from where you want to run the CONCEPT2XIL command. The xilinx.pff file located in the directory where you run CONCEPT2XIL takes precedence over the xilinx.pff file located in $XILINX/cadence/data.

   ---

2. Edit the xilinx.pff file to include new properties. If your path is set up properly, the next time you start Concept it uses the xilinx.pff file in your Cadence working directory as the primary file.
   
   

For more information on the format of the xilinx.pff property filter file, see the “XILINX.PFF Property Filter File Format” appendix.

When you enter a new property in the xilinx.pff file, you must ensure that you have the proper format. Because the set capslock_off variable is set up in the startup.concept file, you must enter property names in lower case. The following shows examples of correct and incorrect entries.

The first column corresponds to the name of the property, while the second column corresponds to the output format of the property when written out to the EDIF netlist.

You see the following in the EDIF netlist written by CONCEPT2XIL.

   (property ts01 (string "dc2s=20ns")
   (property TS03 (string "from:pads:to:pads:30ns")

In the schematic file, logic.1.1, you can see the following.

   FORCEPROP 2 LAST TS01 dc2s=20ns
   FORCEPROP 2 LAST TS02 DP2P=30ns
   FORCEPROP 2 LAST TS03 from:pads:to:pads:30ns
   FORCEPROP 2 LAST TS04 from:ffs:to:pads:20ns
   FORCEPROP 2 LAST TS05 from:pads:to:ffs:20ns

The .edf file does not include TS02, TS04, and TS05 because these entries are incorrectly entered in the xilinx.pff file (upper case instead of lower case).

To translate the property to EDIF, enter its name in lower case in the first column of xilinx.pff. An upper case name does not translate because the netlister cannot find a match in the xilinx.pff file with what writes out to the logic drawing (schematic file).

The second column of the xilinx.pff file determines how the property appears when it writes to the EDIF file. Upper-case entries in the second column cause the EDIF file to use upper case. Lower-case entries in the second column cause the EDIF file to use lower case.

Xilinx Properties Without Values

In Concept, enter all properties with the following syntax.

property_name=value

Xilinx properties such as COLLAPSE, DECODE, DOUBLE, FAST, ID, KEEP, MEDDELAY, NODELAY, NOREDUCE, SLOW, USE_RLOC, and WIREAND inherently associate with a value of TRUE or FALSE, defined as Boolean properties in the xilinx.pff file. Set these Boolean properties to a value of TRUE, for example, FAST=TRUE.

Xilinx Properties on Pads

In Concept, pads are comment bodies; they only exist for documentation purposes.

Xilinx properties on PADS do not translate into the EDIF netlist when you run CONCEPT2XIL. As a workaround, you must use LOC properties attached to the corresponding I/O buffers. The type of LOC properties you must specify on I/O buffers depends on the Package type. For example, normally LOC=P17 implies Pin 17, but for Pin and Ball Grid arrays (PG and BGA packages), a pin mnemonic such as B3 or T1 is used. Refer to the “Attributes, Constraints, and Carry Logic” chapter in the Xilinx Libraries Guide.

Supported Xilinx Properties

For a complete description of the Xilinx properties supported in this release, refer to the “Attributes/Logical Constraints” section in the Libraries Guide.

Obsolete Xilinx Properties

The following table lists Xilinx properties previously valid software versions no longer supported in the new design flow.

Table 3_3 Obsolete Xilinx Properties

Entering Timing Specifications in Schematics

The Cadence netlist writer program (CONCEPT2XIL) converts all property names to lower case letters, and the Xilinx netlist reader EDIF2NGD then converts the property names to uppercase letters. To ensure references from one constraint to another process correctly, observe these guidelines.

• TSidentifier names contain only upper case letters on a Concept schematic (TSMAIN, for example, but not TSmain or TSMain).
  
  
• TSidentifier names referenced in property values require only upper case letters.
  
  

For example, you must enter the TSID1 in the second constraint shown below in upper case letters to match the TSID1 name in the first constraint.

TSID1 = FROM: gr1: TO: gr2: 50;
TSMAIN = FROM: here: TO: there: TSID1: /2;

Creating New Groups from Existing Groups

The Cadence netlist writer program (CONCEPT2XIL) converts all property names to lower case letters, and the Xilinx netlist reader EDIF2NGD then converts the property names to upper case letters. To ensure references from one constraint to another process correctly, observe these guidelines.

• Group names contain only upper case letters on a Cadence schematic (MY_FLOPS, for example, but not my_flops or My_flops).
  
  
• Group names appearing in property values require upper case letters.
  
  

For example, you must enter the GROUP3 shown below in the first constraint example in upper-case letters to match the GROUP3 in the second constraint.

TIMEGRP GROUP1 = gr2: GROUP3;
TIMEGRP GROUP3 = FFS: except: grp5;