The OSC (X3000A/L), OSC4 (XC4000E/L/EX/XL/XV) and OSC5 (XC5200) oscillator components do not have Verilog simulation models associated with them. In the case of the OSC, the clock signal frequency derives from an external crystal-controlled oscillator. On the other hand, use the OSC4 and OSC5 internal oscillators in applications where timing is not critical.
To simulate these oscillators, you must reference the net attached to the output of the oscillator component. Toggle this net at the desired frequency in your Verilog test fixture using a “force” command within an “always” block.
For example, given an oscillator output net called “osclk” attached to an oscillator symbol (OSC, OSC4, or OSC5), and assuming a timescale unit of 1ns, use the following “always” block to emulate an oscillator with a 10 Mhz clock frequency.
always #100 force osclk = ~osclk;
