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Using LogiBLOX

LogiBLOX allows you to quickly synthesize modules for common functions such as adders, counters, and multiplexers. The tool allows you to create components of arbitrary bus width (for example, a 17-bit adder) and automatically uses the best architectural resources for a particular target device family. In this optional section, you replace the ADSU4 component in the ALU1 schematic with a LogiBLOX adder. If you choose to leave the ALU1 schematic in its original form, read this section but do not make any changes.

NOTE

With the M1 release of the Xilinx tool set you must take some special steps to integrate LogiBLOX symbols into the Concept schematic.

Creating a LogiBLOX Module

To replace the ADSU4 symbol with a LogiBLOX module, use the following procedure.

  1. Bring the ALU1 schematic into view (edit alu1).

  2. Select Delete mode, then select the ADSU4 component to delete the symbol from the schematic.

  3. From your UNIX prompt, with your M1 environment set up and within the design's Project Directory, enter the following command.

    lbgui &

    This invokes the LogiBLOX GUI. If running LogiBLOX for the first time from this directory, you get a Setup menu, as shown in the next figure.

    Figure 9.35 LogiBLOX Setup Menu

  4. Specify the parameters for the LogiBLOX module.

    1. Select “cadence” as the vendor and B<I> as the bus notation format.

    2. Select your Project Directory by clicking on the Project Directory tab on the Setup popup. Either type in the location of your project, or use the Browse button to navigate to the desired directory.

    3. Select the Device Family (for example, XC4000E) by clicking on the Device Family tab, then on the arrow button to select the desired device family from the list of supported device families.

    4. Click on Options and select the desired simulation model (usually Structural Verilog). The Verilog netlist generates to support functional simulation and to generate the symbol body for the LogiBLOX module. Ensure the selection of the NGO file as the Implementation Netlist. You do not use the Component Declaration option on a top level schematic.

      Figure 9.36 LogiBLOX setup

    5. Click on OK to accept these settings.

  5. The LogiBLOX Module Selector appears. Set the options in this dialog box as shown in the “Using the LogiBLOX Module Selector” figure. Make a non-registered adder/subtractor module of four bits. Name the component “addsub4.”

    Figure 9.37 Using the LogiBLOX Module Selector

  6. Click OK. LogiBLOX generates a Verilog netlist and an NGO file for this new module after a slight delay. You need this NGO file to do the implementation in M1.

  7. After LogiBLOX successfully creates the module, exit LogiBLOX by clicking the left mouse button on the Cancel button.

Creating a Symbol for the LogiBLOX Module

Because this tutorial is schematic based, you must create a symbol for the LogiBLOX module. You must create the symbol manually from within Concept using the genview command.

  1. Make sure the V file for your LogiBLOX module resides in your Project directory. Enter the following command in the Concept message window to generate the body.

    genview -i  logiblox_module_name.v -v logic \
    body verilog

    Assuming you used the suggested name of addsub4, issue the following command.

    genview -i  addsub4.v -v logic body verilog

    This command tells Concept to generate a body view for a module named addsub4 from the Verilog netlist, and to put it in the logical view for this module.

  2. After the module generates, edit the resulting verilog.v file in the addsub4/logic/  subdirectory of the new module directory by opening the file in a text editor and adding the following directive after the module declaration.

    parameter cds_action = “ignore”;

  3. In Concept, in the ALU1 schematic, add the ADDSUB4 module (“add addsub4”) and connect it as shown in the next figure.

Figure 9.38 Adding the ADDSUB4 LogiBLOX Component

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