Installing the Tutorial

This tutorial demonstrates the Alliance Series Design Implementation Tools flow. The tutorial design is a simple 8-bit counter with asynchronous clear and clock enable. The design is compiled with Synopsys FPGA Express and is described by a Xilinx Netlist File (XNF). The tutorial passes an input netlist from FPGA Express to the Alliance Series Design Implementation Tools, and incorporates timing and placement constraints through a User Constraints File (UCF).

First, create an empty working directory. In this tutorial, the newly created directory is named Count. Next, copy the following files from the /userware/tutorial/qstart/ directory located on the Alliance Series Design Implementation Tools CD-ROM to your newly created working directory.

NOTE

The source code (count8.vhd) is also available for reference.