This section describes the common components that are found on the FPGA Demonstration Board. The following figure shows the component layout of the FPGA Demonstration Board.
Figure 1.2 FPGA Demonstration Board |  |
A regulated +5 volts and ground connected to the FPGA Demonstration Board through connector J9. Pin 1 (square pad) is +5 V and pin 2 is ground. The power supply should provide at least 250 mA of current to drive the LED displays.
This input provides a way to power the FPGA Demonstration Board from an unregulated source, such as a 9 V battery or an AC adapter. Typically, the input should be 7VDC - 12VDC at 250 mA. You must consider the power dissipation requirements of the U3 voltage regulator if the voltage input is greater than 9 V.
The J12 unregulated power input provides two holes to connect the unregulated power source. The hole with the square pad, marked with a "+" is the positive input. The other hole, marked with a "-" is circuit ground. The positive input is connected through the power on-off switch SW2-1 to U3-1, which is the optional +5 V regulator. U3 must be installed to use this input.
You can install a three terminal +5 V regulator, such as the LM2940CT shown in the “LM2940CT +5 V Regulator” figure. This regulator powers the demonstration board from an unregulated power supply, such as a +9 V battery. Pin 1 (square pad) is Vin, pin 2 is ground, and pin 3 is +5 V out.
Insulate the metal heat sink tab of the regulator from traces and vias on the PCB.
Figure 1.3 LM2940CT +5 V Regulator | |
Depending on how the Reset signal routing is configured the RESET pushbutton switch can apply an active-Low Reset signal to the FPGAs and configuration PROMs. Reset is normally pulled High through a 27 kilohm resistor.
The SPARE pushbutton applies an active-Low signal to the XC3020A on pin 16, and to the XC4003E on pin 18. You can isolate these pins from the switch by using the trace-cut options on the solder side of the board. The trace-cut options appear as point-to-point triangles; the trace-cut option for the XC3020A is under its socket and the trace-cut option for the XC4003E is under R3. The SPARE signal is pulled High through a 27 kilohm resistor.
The PROG pushbutton applies an active-Low signal to the DONE/PROGRAM input on the XC3020A FPGA socket at pin 45 and to the PROGRAM input on the XC4003E FPGA socket at pin 55. The PROG signal is normally pulled High through a 13.5 kilohm resistor.
Eight switches connect to eight general-purpose inputs on both the XC3020A and the XC4003E FPGAs. These switches provide logic input to the FPGAs. An FPGA input pin is set to a logic "1" when a switch is on, and a logic "0" when a switch is off. See the following figure for a diagram.
Figure 1.4 FPGA Demonstration Board General-Purpose Switch | |
The FPGA pins connected to this switch are intended for use as inputs. However, each FPGA pin has a 1 kilohm resistor that isolates it from the switch, so it is possible to define the pins as outputs. You can also drive the pins from an external source by connecting that signal to the FPGA probe point header. The following table lists the FPGA pin connections.
| Switch | XC3020A | XC4003E |
| SW3-1 | 11 | 19 |
| SW3-2 | 13 | 20 |
| SW3-3 | 15 | 23 |
| SW3-4 | 17 | 24 |
| SW3-5 | 19 | 25 |
| SW3-6 | 21 | 26 |
| SW3-7 | 23 | 27 |
| SW3-8 | 24 | 28 |
Three seven-segment displays are included with the leftmost display (U6) connect to the XC3020A FPGA. The rightmost two displays (U7 and U8) connect to the XC4003E device.
Each LED segment is turned on by driving the corresponding FPGA pin `LOW' with a logic `0.' The decimal point on U8 connects to the INIT pin of the XC4003E (pin 41) and serves as a programming error indicator. The decimal point should be on while the FPGA is in its internal clearing state, then it should remain off during configuration. If the decimal point comes back on, a programming error has occurred.
The decimal points on U6 and U7 are tied to the Low During Configuration (LDC) pins of the XC3020A and XC4003E, respectively. The decimal points are on while the FPGAs wait to be configured.
The following table, "Seven-Segment I/O Connections" shows the I/O pin definitions. The “Seven-Segment Display” figure shows the seven-segment display of the FPGA demonstration board.
| Display Segment | XC3020A | XC4003E | XC4003E |
| U6 | U7 | U8 | |
| a | 38 | 39 | 49 |
| b | 39 | 38 | 48 |
| c | 40 | 36 | 47 |
| d | 56 | 35 | 46 |
| e | 49 | 29 | 45 |
| f | 53 | 40 | 50 |
| g | 55 | 44 | 51 |
| decimal point | 30 | 37 | 41 |
Figure 1.5 Seven-Segment Display | |
Eight LEDs are connected to the I/O pins of each FPGA. Pins D1 through D8 connect to the XC3020A, and D9 through D16 connect to the XC4003E. You can turn on an LED by driving its corresponding FPGA pin Low with a logic "0." The following table shows the pin connections for the LED indicators.
| LED | XC3020A Pin | LED | XC4003E Pin |
| D1 | 37 | D9 | 61 |
| D2 | 36 | D10 | 62 |
| D3 | 41 | D11 | 65 |
| D4 | 33 | D12 | 66 |
| D5 | 32 | D13 | 57 |
| D6 | 31 | D14 | 58 |
| D7 | 28 | D15 | 59 |
| D8 | 29 | D16 | 60 |
There are 16 I/O lines that connect the XC3020A and XC4003E FPGAs. These are shown in the following table.
| I/O Line | XC3020A Pin | XC4003E Pin |
| 0 | 61 | 10 |
| 1 | 62 | 9 |
| 2 | 63 | 8 |
| 3 | 64 | 7 |
| 4 | 65 | 6 |
| 5 | 66 | 5 |
| 6 | 67 | 4 |
| 7 | 68 | 3 |
| 8 | 2 | 84 |
| 9 | 3 | 83 |
| 10 | 4 | 82 |
| 11 | 5 | 81 |
| 12 | 6 | 80 |
| 13 | 7 | 79 |
| 14 | 8 | 78 |
| 15 | 9 | 77 |
You can add a standard 4-pin crystal oscillator to the FPGA Demonstration Board. The oscillator output drives the XC3020A XTL2 input at pin 43 and the XC4003E PGCK1 input at pin 13.
The Prototype area is a 0.1-inch grid of holes where you can add additional circuitry to the demonstration board. A +5 V bus (component side) and a ground bus (solder side) are available on the perimeter of this area. There are also locations for filter capacitors.
