You need to provide JEDEC files for each XC9500 device, BIT files for each Xilinx FPGA device in the JTAG programming chain, and BSDL files for the remaining devices.
JEDEC files are XC9500 CPLD programming files generated by the Xilinx CPLD fitter. They are ASCII text files containing programming information and, optionally, functional test vectors that can be used to verify the correct functional behavior of the programmed device. One JEDEC file is required for each XC9500 device in the JTAG programming chain.
Use the device properties (File 
Properties) dialog to specify the location of JEDEC files for each XC9500 device. The name of the JEDEC file is assumed to be <design name>.jed, but can be specified exactly by the user.
The Boundary-Scan Description Language (BSDL) files use a subset of VHDL to describe the boundary scan features of a device. The JTAG Programmer automatically extracts the length of the instruction register from the BSDL file to place non-XC9500 devices in bypass mode. One user-provided BSDL file is required for each type of non-XC9500 device in the JTAG programming chain. XC9500 BSDL files are located automatically by the JTAG Programmer.
Use the device properties dialog to specify the location of BSDL files for non-XC9500 devices. The name of the BSDL file is assumed to be <device name>.bsd.
Bit files are Xilinx FPGA configuration files generated by the Xilinx FPGA design software. They are proprietary format binary files containing configuration information. One BIT file is required for each Xilinx FPGA in the JTAG boundary-scan chain.
Use the device properties (File Properties) dialog to specify the location of the BIT files for each Xilinx FPGA device. The required extension for BIT files is .bit.
