Connecting Devices in a Boundary-Scan Chain

All devices in the chain share the TCK and TMS signals. The system TDI signal is connected to the TDI input of the first device in the boundary-scan chain. The TDO signal from that first device is connected to the TDI input of the second device in the chain and so on. The last device in the chain has its TDO output connected to the system TDO pin. This configuration is illustrated in Figure 4-1.

Figure 4.1 Single Port Serial Boundary-Scan Chain

Design Rules for Boundary-Scan and ISP Systems

The boundary-scan standard requires pull-up resistance to be supplied internally to the TDI and TMS pins by the chips, but no particular value is required. This allows vendors supply whatever they choose and still remain in full compliance. Because of this, very long boundary-scan chains, or chains using parts from multiple vendors, may present significant loading to the ISP drive cable. In these cases:

1. Use the latest Xilinx download cables (parallel cables with serial numbers greater than 5000, or any X-Checker cable).
   
   
2. Consider including buffers on TMS or TCK signals interleaved at various points on your JTAG circuitry to account for unknown device impedance.
   
   Some users have noted that their designs appear to experience erase time or programming time extension as the design progresses, particularly for long chains. This is probably due to switching noise.
   
   
3. Put the rest of the JTAG chain into HIGHZ mode by selecting the HIGHZ preference on JTAG Programmer when programming a troublesome part.
   
   This will limit the number of additional signals presented to the system and the troublesome part.
   
   
4. If free running clocks are delivered into boundary-scan devices, it may be necessary to disconnect or disable their entry into these devices during ISP or boundary-scan operations.
   
   Charge pumps, the heart of the XC9500 ISP circuitry, require a modest amount of care. The voltages to which the pumps must rise are directly derived from the external voltage supplied to the VCCINT pins on the XC9500 parts. Because these elevated voltages must be within their prescribed values to properly program the CPLD, it is vital that they be provided with very clean (noise free) voltage within the correct range. This suggests the first two key rules:
   
   
5. Make sure VCC is within the rated value: 5V +/- 5%.
   
   
6. Provide both 0.1 and 0.01 uF capacitors at every VCC point of the chip, and attached directly to the nearest ground.