Xilinx recommends that all the mode pins of the devices be tied low before starting the configuration. This is recommended for all XC4000, XC5000 and Spartan device families.
In order to enable the boundary-scan circuitry in the device, you must install a pull down resistor on the INIT pin. The value of the pull down should be selected so as to draw the INIT pin to approximately 0.5V. Typically a pull down of approximately 1KOhm should accomplish this.
The XC4000 (not the XLA and XV), XC5000 and Spartan (not the SpartanXL) devices freeze if data errors occur during boundary-scan configuration. The only method for unlocking the frozen device is to reset the power to the device or pulse the PROGRAM pin low. (This latter method would have to be accomplished manually since the download cables (when being used for boundary-scan operations), do not have control over the PROGRAM pin. Although this situation is rare, it is possible to design your system so as to detect if that condition has occurred. The JTAG Programmer software allows you to check for this in three ways:
1. Assume successful verification - since it is a low probability event, simply configure the device and run. The drawback is that the failure of the device is then only detected at run-time.
2. Readback verify the configuration memory - after configuring, readback the contents of the configuration memory and check against the source bitstream file. If the device has frozen, the returned bits will be incorrect. Since bit files can be large, this might be time consuming.
3. Tie a free pin on the device to ground - after configuring, the software will perform an EXTEST instruction to read the device pin value. If the device has locked up, the pin value will not be read correctly.
Any verify operation executed immediately after configuration without boundary-scan functionality enabledwill fail because the test access port no longer exists. Always remember to instantiate the BSCAN symbol for reliable operation of your devices.
The implementation of boundary-scan based configuration of FPGAs precludes the use of concurrent ISP. For this reason, the concurrent mode preference is disabled (or ignored) when FPGAs are selected to be operated upon.
