The startup file for the Synopsys synthesis tools is .synopsys_dc.setup. This file contains the search path for the XSI libraries, Synopsys libraries, and user libraries. XSI provides a template Synopsys startup file.
XSI provides the template.synopsys_dc.setup_dc and template.synopsys_dc.setup_fc template files. You can find the template files in the $XILINX/synopsys/examples directory. Use template.synopsys_dc.setup_dc if you use Design Compiler; use template.synopsys_dc.setup_fc if you use FPGA Compiler.
$SYNOPSYS is the directory where the Synopsys software resides. If you do not know the location of this directory, enter the following at the system prompt.
echo $SYNOPSYS
If you already have a .synopsys_dc.setup file, you must modify your file to include the commands found in the Xilinx-supplied template startup files.
If you do not already have a Synopsys startup file, copy the appropriate Xilinx-supplied startup file to your home or working directory and rename it as follows.
cp $XILINX/synopsys/examples/ template.synopsys_dc.setup_compiler .synopsys_dc.setup
Substitute “dc” or “fc” for compiler.
This section contains a reproduction of the template setup file for FPGA Compiler.
/* =================================================================== */
/* Template .synopsys_dc.setup file for Xilinx designs */
/* For use with Synopsys FPGA Compiler. */
/* =================================================================== */
/* =================================================================== */
/* The Synopsys search path should be set to point */
/* to the directories that contain the various */
/* synthesis libraries used by FPGA Compiler during */
/* synthesis. */
/* =================================================================== */
XilinxInstall = get_unix_variable(XILINX);
SynopsysInstall = get_unix_variable(SYNOPSYS);
search_path = { . \
XilinxInstall + /synopsys/libraries/syn \
SynopsysInstall + /libraries/syn }
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* Ensure that your UNIX environment */
/* includes the two environment var- */
/* iables: $XILINX (points to the */
/* Xilinx installation directory) and*/
/* $SYNOPSYS (points to the Synopsys */
/* installation directory.) */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* ================================================= */
/* Define a work library in the current project dir */
/* to hold temporary files and keep the project area */
/* uncluttered. Note: You must create a subdirectory */
/* in your project directory called WORK. */
/* ================================================= */
define_design_lib WORK -path ./WORK
/* ================================================= */
/* General configuration settings. */
/* ================================================= */
compile_fix_multiple_port_nets = true
xnfout_constraints_per_endpoint = 0
xnfout_library_version = "2.0.0"
bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"
/* ================================================= */
/* Set the link, target and synthetic library */
/* variables. Use synlibs (with the -fc switch) to */
/* determine the link and target library settings. */
/* You may like to copy this file to your project */
/* directory, rename it ".synopsys_dc.setup" and */
/* append the output of synlibs. For example: */
/* synlibs -fc 4028ex-3 >> .synopsys_dc.setup */
/* ================================================= */
This section shows the template setup file for Design Compiler.
/* =================================================================== */
/* Template .synopsys_dc.setup file for Xilinx designs */
/* For use with Synopsys Design Compiler. */
/* =================================================================== */
/* =================================================================== */
/* The Synopsys search path should be set to point */
/* to the directories that contain the various */
/* synthesis libraries used by Design Compiler during */
/* synthesis. */
/* =================================================================== */
XilinxInstall = get_unix_variable(XILINX);
SynopsysInstall = get_unix_variable(SYNOPSYS);
search_path = { . \
XilinxInstall + /synopsys/libraries/syn \
SynopsysInstall + /libraries/syn }
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* Ensure that your UNIX environment */
/* includes the two environment var- */
/* iables: $XILINX (points to the */
/* Xilinx installation directory) and*/
/* $SYNOPSYS (points to the Synopsys */
/* installation directory.) */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
/* ================================================= */
/* Define a work library in the current project dir */
/* to hold temporary files and keep the project area */
/* uncluttered. Note: You must create a subdirectory */
/* in your project directory called WORK. */
/* ================================================= */
define_design_lib WORK -path ./WORK
/* ================================================= */
/* General configuration settings. */
/* ================================================= */
compile_fix_multiple_port_nets = true
bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"
edifout_netlist_only = true
edifout_power_and_ground_representation = cell
edifout_write_properties_list = "instance_number pad_location part"
edifout_no_array = true
/* ================================================= */
/* Set the link, target and synthetic library */
/* variables. Use synlibs (with the -dc switch) to */
/* determine the link and target library settings. */
/* You may like to copy this file to your project */
/* directory, rename it ".synopsys_dc.setup" and */
/* append the output of synlibs. For example: */
/* synlibs -dc 4028ex-3 >> .synopsys_dc.setup */
/* ================================================= */
