Each primitive library contains device and speed-grade specific estimated pre-layout and routing wire-load models. The Synopsys tools can use these estimates when optimizing your design for an FPGA. XSI provides two wire-load models per device-speed grade combination, an average model and a worst-case model. These models receive “_avg” and “_wc” designations, respectively; the default is average. Using the default (average) wire loads produces more realistic designs.
To change a wire load model, use the following syntax.
set_wire_load “parttype -s.wc”
Substitute the part type to change for parttype.
Run Synlibs with the -h option to get a listing of all available part type and speed grade combinations. You can also refer to the Xilinx online Data Book at http://www.xilinx.com for current speed grade information.
