Recommended VSS Simulation Strategy

Because of the flexibility of the simulation environment, you can verify your design using various methods. The following steps, explained in subsequent sections, show you one recommended flow for FPGA simulation.

1. Create a .synopsys_vss.setup file.
   
   Before you can begin simulation, you must create a simulation setup file.
   
   
2. Specify the initial states of your registers in your VHDL source file.
   
   If you use attributes at the DC Shell command line or in Design Analyzer to control the initial states of the registers in your design, RTL simulation does not reflect those initial states.
   
   
3. Create a test bench file.
   
   By following the guidelines described in this section, you can use the same test bench for both RTL and timing simulation.
   
   
4. Perform RTL simulation.
   
   This step allows you to debug the behavior of your source design before implementing it in an FPGA.
   
   
5. Implement the design in an FPGA.
   
   This step provides the necessary physical resource information necessary for timing simulation.
   
   
6. Prepare the timing model.
   
   The NGD2VHDL program prepares a back-annotated timing model of your design for simulation.
   
   
7. Perform timing simulation.
   
   By re-using the RTL simulation test bench file, you can easily compare results and prevent errors caused by accidental differences between separate test bench files.