Editing the VSS Setup File
To properly analyze and simulate Xilinx designs using VSS, you must edit your Synopsys VSS setup file, .synopsys_vss.setup. You can find a sample VSS setup file in $XILINX/synopsys/examples/template.synopsys_vss. setup. You can copy this file to your project directory and rename it .synopsys_vss.setup.
The following example shows the sample VSS setup file in $XILINX/synopsys/examples/template.synopsys_vss. setup. Make sure you have included the information in this file in your VSS setup file.
-- =================================================== --
-- Template .synopsys_vss.setup file for Xilinx design --
-- For use with Synopsys VSS. --
-- =================================================== --
-- =================================================== --
-- Set any simulation preferences. --
-- =================================================== --
TIMEBASE = NS
TIME_RES_FACTOR = 0.1
-- ================================================== --
-- Define a work library in the current project dir --
-- to hold temporary files and keep the project area --
-- uncluttered. Note: You must create a subdirectory --
-- in your project directory called WORK. --
-- ================================================== --
WORK > DEFAULT
DEFAULT : ./WORK
-- ================================================== --
-- Note that the following simulation libraries are --
-- provided ready-analyzed with VSS 3.4b-vital. (With --
-- the exception of FTGS libraries which are ready- --
-- analyzed with VSS 3.4b) If you're using a later --
-- version of VSS then refer to the automatic compile --
-- scripts provided in the appropriate library's --
-- source directory. I.e. $XILINX/synopsys/sim/src --
-- ================================================== --
-- ================================================== --
-- VITAL SimPrim libraries provided to support back- --
-- annotated simulation only. --
-- ================================================== --
SIMPRIM : $XILINX/synopsys/libraries/sim/lib/simprims
-- ================================================== --
-- Packages used by LogiBLOX functional simulation --
-- models only. Ie. To support behavioral simulation --
-- of VHDL designs with instantiated LogiBLOX cells. --
-- ================================================== --
LOGIBLOX : $XILINX/synopsys/libraries/sim/lib/logiblox
-- ================================================== --
-- Example pointers to the Xilinx FTGS simulation --
-- libraries. Note that these libraries are provided --
-- for compatibility with earlier versions of XSI. --
-- ================================================== --
XC4000E : $XILINX/synopsys/libraries/sim/lib/xc4000e/ftgs
XC5200 : $XILINX/synopsys/libraries/sim/lib/xc5200/ftgs
XC7000 : $XILINX/synopsys/libraries/sim/lib/xc7000/ftgs
XC9000 : $XILINX/synopsys/libraries/sim/lib/xc9000/ftgs
