This appendix contains definitions and explanations for terms used in the Foundation Series Quick Start Guide 1.5.
ABEL is a high-level language (HDL) and compilation system produced by Data I/O Corporation.
In state machines, actions are HDL statements that are used to make assignments to output ports or internal signals. Actions can be executed at several points in a state diagram. The most commonly used actions are state actions and transition actions. State actions are executed when the machine is in the associated state. Transition actions are executed when the machine goes through the associated transition.
An Electronic Design Automation (EDA) vendor. Aldec provides the Foundation Project Manager, Schematic Editor, Logic Simulator, and HDL Editor.
Aliases, or signal groups, are useful for probing specific groups of nodes.
The Foundation Express process in which design source files are examined for correct syntax.
Architecture is the common logic structure of a family of programmable integrated circuits. The same architecture can be realized in different manufacturing processes. Examples of Xilinx architectures are the XC4000, XC5200, and XC9500 devices.
Attributes are instructions placed on symbols or nets in an FPGA schematic to indicate their placement, implementation, naming, direction, or other properties.
Back-annotation is the translation of a routed or fitted design to a timing simulation netlist.
A program that produces a bitstream for Xilinx device configuration. BitGen takes a fully routed NCD (Circuit Description) file as its input and produces a configuration bitstream, a binary file with a .bit extension.
Instantiation where the synthesizer is not given the architecture or modules. In Foundation, black boxes are translated with the implementation tools.
A breakpoint is a condition for which a simulator must stop to perform simulation commands.
A buffer is an element used to increase the current or drive of a weak signal and, consequently, increase the fanout of the signal. A storage element.
A bus is a group of nets carrying common information. In LogiBLOX, bus sizes are declared so that they can be expanded accordingly during design implementation.
The Configurable Logic Block (CLB). Constitutes the basic FPGA cell. It includes two 16-bit function generators (F or G), one 8-bit function generator (H), two registers (flip-flops or latches), and reprogrammable routing controls (multiplexers).
CLBs are used to implement macros and other designed functions. They provide the physical support for an implemented and downloaded design. CLBs have inputs on each side, and this versatility makes them flexible for the mapping and partitioning of logic.
A component is an instantiation or symbol reference from a library of logic elements that can be placed on a schematic.
If there is more than one transition leaving a state in a state machine, you must associate a condition with each transition. A condition is a Boolean expression.
Constraints are specifications for the implementation process. There are several categories of constraints: routing, timing, area, mapping, and placement constraints.
Using attributes, you can force the placement of logic (macros) in CLBs, the location of CLBs on the chip, and the maximum delay between flip-flops. CLBs are arranged in columns and rows on the FPGA device. The goal is to place logic in columns on the device to attain the best possible placement from the standpoint of both performance and space.
A GUI tool that you can use to enter design constraints. In Foundation 1.5, there are two constraint editors. The Express editor is available only in the Foundation Express product configuration. The Xilinx Constraints Editor is integrated with the Design Implementation tools and available in all product configurations.
A constraint file specifies constraints (location and path delay) information in a textual form. An alternate method is to place constraints on a schematic.
A software tool for generating and delivering parameterizable cores optimized for FPGAs. The library includes cores as complex as DSP filters and multipliers, and as simple as delay elements. You can use these cores as building blocks in order to complete your designs more quickly.
Complex Programmable Logic Device (CPLD) is an erasable programmable logic device that can be programmed with a schematic or a behavioral design. CPLDs constitute a type of complex PLD based on EPROM or EEPROM technology. They are characterized by an architecture offering high speed, predictable timing, and simple software.
The basic CPLD cell is called a macrocell, which is the CPLD implementation of a CLB. It is composed of AND gate arrays and is surrounded by the interconnect area.
CPLDs consume more power than FPGA devices, are based on a different architecture, and are primarily used to support behavioral designs and to implement complex counters, complex state machines, arithmetic operations, wide inputs, and PAL crunchers.
The CPLD Fitter implements designs for the XC9500 devices.
A set of tools accessible from the Project Manager. These tools include the Schematic Editor, State Editor, and HDL Editor.
Foundation Express, an embedded portion of the Foundation software package, contains the VHDL and Verilog design languages.
A daisy chain is a series of bitstream files concatenated in one file. It can be used to program several FPGAs connected in a daisy chain board configuration.
A set of tools that comprise the mainstream programs offered in the Xilinx design implementation tools. The tools are NGDBuild, MAP, PAR, NGDAnno, TRCE, all the NGD2 translator tools, BitGen, PROMGen, and EPIC. The GUI-based tools are Flow Engine, Constraint Editor, and Template Manager.
Xilinx Foundation 1.4 graphical user interface for managing and implementing designs. In Foundation 1.4, the Design Manager is accessed by selecting the Implement M1 button from the Project Manager. (For Xilinx Foundation 1.5 series, the Project Manager replaces the Design Manager.)
Effort level refers to how hard the Xilinx Design System (XDS) tries to place a design. The effort level settings are.
The HDL process that combines the individual parts of a into a single design and then synthesizes the design.
EXORmacs is a PROM format supported by the Xilinx tools. Its maximum address is 16 777 216. This format supports PROM files of up to (8 x 16 777 216) = 134 217 728 bits.
Fanout is the maximum number of specified unit loads that a specified output can drive.
The fitter is the software that maps a PLD logic description into the target CPLD.
Floorplanning is the process of choosing the best grouping and connectivity of logic in a design.
It is also the process of manually placing blocks of logic in an FPGA where the goal is to increase density, routability, or performance.
Field Programmable Gate Array (FPGA), is a class of integrated circuits pioneered by Xilinx in which the logic function is defined by the customer using Xilinx development system software after the IC has been manufactured and delivered to the end user. Gate arrays are another type of IC whose logic is defined during the manufacturing process. Xilinx supplies RAM-based FPGA devices.
FPGA applications include fast counters, fast pipelined designs, register intensive designs, and battery powered multi-level logic.
Functional simulation is the process of identifying logic errors in your design before it is implemented in a Xilinx device. Because timing information for the design is not available, the simulator tests the logic in the design using unit delays. Functional simulation is usually performed at the early stages of the design process.
A gate is an integrated circuit composed of several transistors and capable of representing any primitive logic state, such as AND, OR, XOR, or NOT inversion conditions. Gates are also called digital, switching, or logic circuits.
Guided design is the use of a previously implemented version of a file for design mapping, placement, and routing. Guided design allows logic to be modified or added to a design while preserving the layout and performance that have been previously achieved.
An existing NCD file is used to “guide” the current MAP run. The guide file may be used at any stage of implementation: unplaced or placed, unrouted or routed. In Release 1.5, guided mapping is supported through the standalone Design Manager.
Hardware Description Language. A language that describes circuits in textual code. The two most widely accepted HDLs are VHDL and Verilog.
An HDL, or hardware description language, describes designs in a technology-independent manner using a high level of abstraction.
Foundation's editor for XABEL, Verilog, and VHDL. The HDL Editor also provides a syntax checker, language templates, and access to the synthesis tools.
Within the Foundation Project Manager, the Synthesis button displays in the Project Flow area if a project is defined as an HDL Flow. In Release 1.5, an HDL Flow supports VHDL and Verilog top-level designs.
A hierarchical design is a design composed of multiple sheets at different levels of your schematic.
The left-hand portion of the Foundation Project Manager that displays the current design project. The browser also displays two tabs, Files and Versions.
Implementation is the mapping, placement and routing of a design. A phase in the design process during which the design is placed and routed. (For CPLDs, the design is fitted.)
Incorporating a macro or module into a top-level design. The instantiated module can be a LogiBLOX module, VHDL module, Verilog module, schematic module, state machine, or netlist.
The Language Assistant in the HDL Editor provides templates to aid you in common VHDL and Verilog constructs, common logic functions, and architecture-specific features.
The Library Manager is the tool used to perform a variety of operations on the design entry tools libraries and their contents. These libraries contain the primitives and macros that you use to build your design.
Lock placement applies a constraint to all placed components in your design. This option specifies that placed components cannot be unplaced, moved, or deleted.
Xilinx design tool for creating high-level modules such as counters, shift registers, and multiplexers.
Logic is one of the three major classes of ICs in most digital electronic systems: microprocessors, memory, and logic. Logic is used for data manipulation and control functions that require higher speed than a microprocessor can provide.
The Logic Simulator, a real-time interactive design tool, can be used for both functional and timing simulation of designs. The Logic Simulator creates an electronic breadboard of your design directly from your design's netlist. The Logic Simulator can be accessed by clicking the Functional Simulation icon on the Simulation phase button or the Timing Simulation icon on the Verification phase button in the Project Manager.
A macro is a component made of nets and primitives, flip-flops or latches, that implements high-level functions, such as adders, subtractors, and dividers. Soft macros and RPMs are types of macros.
A macro can be unplaced, partially placed, or fully placed; it can also be unrouted, partially routed, or fully routed. See also “physical macro.”
Mapping is the process of assigning a design's logic elements to the specific physical elements that actually implement logic functions in a device.
An MCS file is an output from the PROMGen program in Intel's MCS-86 format.
An MRP (mapping report) file is an output of the MAP run. It is an ASCII file containing information about the MAP run. The information in this file contains DRC warnings and messages, mapper warnings and messages, design information, schematic attributes, removed logic, expanded logic, signal cross references, symbol cross references, physical design errors and warnings, and a design summary.
An NCD (netlist circuit description) file is the output design file from the MAP program, LCA2NCD, PAR, or EPIC. It is a flat physical design database correlated to the physical side of the NGD in order to provide coupling back to the user's original design. The NCD file is an input file to MAP, PAR, TRCE, BitGen, and NGDAnno.
A net is a logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.
A net is an electrical connection between components or nets. It can also be a connection from a single component. It is the same as a wire or a signal.
A netlist is a text description of the circuit connectivity. It is basically a list of connectors, a list of instances, and, for each instance, a list of the signals connected to the instance terminals. In addition, the netlist contains attribute information.
An NGA (native generic annotated) file is an output from the NGDAnno run. An NGA file is subsequently input to the appropriate NGD2 translation program.
The NGDAnno program distributes delays, setup and hold time, and pulse widths found in the physical NCD design file back to the logical NGD file. NGDAnno merges mapping information from the NGM file, and timing information from the NCD file and puts all this data in the NGA file.
The NGDBuild program performs all the steps necessary to read a netlist file in XNF or EDIF format and create an NGD file describing the logical design. The GUI equivalent is called Translate.
An NGD (native generic database) file is an output from the NGDBuild run. An NGD file contains a logical description of the design expressed both in terms of the hierarchy used when the design was first created and in terms of lower-level Xilinx primitives to which the hierarchy resolves.
An NGM (native generic mapping) file is an output from the MAP run and contains mapping information for the design. The NGM file is an input file to the NGDAnno program.
For state machines, in one-hot encoding, an individual state register is dedicated to one state. Only one flip-flop is active, or hot, at any one time.
Optimization is the process that decreases the area or increases the speed of a design. Foundation allows you to control optimization of a design on a module-by-module basis. This means that you have the ability to, for instance, optimize certain modules of your design for speed, some for area, and some for a balance of both.
The third step in the FPGA Express synthesis flow. In this stage, the implemented design is re-synthesized with constraints the user specifies. This is the final step before writing out the XNF file from FPGA Express.
PAR is a program that takes an NCD file, places and routes the design, and outputs another NCD file. The NCD file produced by PAR can be used as a guide file for reiterative placement and routing. The NCD file can also be used by the bitstream generator, BitGen.
A path delay is the time it takes for a signal to propagate through a path.
The PCF file is the “Physical Constraints File” created by the MAP program. It is an ASCII file containing physical constraints created by the MAP program as well as physical constraints you enter. You can edit the PCF file from within EPIC.
Project Description File. The PDF file contains library and other project-specific information. Not to be confused with an Adobe Acrobat document with the same extension.
Physical Design Rule Check (DRC) is a series of tests to discover logical and physical errors in the design. Physical DRC is applied from EPIC, BitGen, PAR, and Hardware Debugger. By default, results of the DRC are written into the current working directory.
A pin can be a symbol pin or a package pin. A package pin is a physical connector on an integrated circuit package that carries signals into and out of an integrated circuit. A symbol pin, also referred to as an instance pin, is the connection point of an instance to a net.
Pinwires are wires which are directly tied to the pin of a site (that is, CLB, IOB).
A PLD, or programmable logic device, is composed of two types of gate arrays: the AND array and the OR array, thus providing for sum of products algorithmic representations. PLDs include three distinct types of chips: PROMs, PALs, and PLAs. The most flexible device is the PLA (programmable logic array) in which both the AND and OR gate arrays are programmable. In the PROM device, only the OR gate array is programmable. In the PAL device, only the AND gate array is programmable. PLDs are programmed by blowing the fuses along the paths that must be disconnected.
FPGAs and CPLDs are classes of PLDs.
The primary GUI for managing a Foundation Project. Design entry, synthesis, simulation, implementation, and downloading can be launched from the Project Manager.
The right-hand portion of the Foundation Project Manager that provides access to the synthesis and implementation tools, and the current design project. The Project Flowchart can display up to four tabs: Flow, Contents, Reports, and Synthesis.
The PROM File Formatter is the program used to format one or more bitstreams into an MC86, TEKHEX, EXORmacs or HEX PROM file format.
A radix is the base - usually binary, octal, decimal, or hexadecimal - in which waveforms are displayed in a waveform viewer.
The process of assigning logical nets to physical wire segments in the FPGA that interconnect logic cells.
A route that can pass through an occupied or an unoccupied CLB site is called a route-through. You can manually do a route-through in EPIC. Route-throughs provide you with routing resources that would otherwise be unavailable.
If a project is defined as a Schematic Flow, no Synthesis button displays in the Project Flow area of the Project Manager. A Schematic Flow may only have schematic designs as top-level designs. However, these top-level designs can contain HDL modules. If the designs contain HDL modules, the Synthesis tab displays in the upper portion of the Project Flow area.
The values stored in the memory elements of a device (flip-flops, RAMs, CLB outputs, and IOBs) that represent the state of that device for a particular readback (time). To each state, there corresponds a specific set of logical values.
A state diagram is a pictorial description of the outputs and required inputs for each state transition as well as the sequencing between states. Each circle in a state diagram contains the name of a state. Arrows to and from the circles show the transitions between states and the input conditions that cause state transitions. These conditions are written next to each arrow.
A state machine is a set of combinatorial and sequential logic elements arranged to operate in a predefined sequence in response to specified inputs. The hardware implementation of a state machine design is a set of storage registers (flip-flops) and combinatorial logic, or gates. The storage registers store the current state, and the logic network performs the operations to determine the next state. See also “symbolic state machine” and “encoded state machine.”
A state table shows the value of the outputs for all combinations of current states and inputs. It also defines the next state for each set of inputs.
A static timing analysis is a point-to-point delay analysis of a design network.
A static timing analyzer is a tool that analyzes the timing of the design on the basis of its paths.
The status bar is an area located at the bottom of a tool window that provides information about the commands that you are about to select or that are being processed.
Stimulus information is the information defined at the schematic level and representing a list of nodes and vectors to be simulated in functional and timing simulation.
Synopsys supports HDL, a behavioral language for entering equations. HDL also enables you to include LogiBLOX schematic components in a design.
The HDL design process in which each design module is elaborated and the design hierarchy is created and linked to form a unique design implementation. Synthesis starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a lower level of logic abstraction using a library containing primitives.
TEKHEX (Tektronix) is a PROM format supported by Xilinx. Its maximum address is 65 536. This format supports PROM files of up to (8 x 65 536) = 524 288 bits.
TRCE (Timing Reporter and Circuit Evaluator) “trace” is a program that will automatically perform a static timing analysis on a design using the specified (either timing constraints. The input to TRCE is an NCD file and, optionally, a PCF file. The output from TRCE is an ASCII timing report which indicates how well the timing constraints for your design have been met.
A TWR (Timing Wizard Report) file is an output from the TRCE program. A TWR file contains a logical description of the design expressed both in terms of the hierarchy used when the design was first created and in terms of lower-level Xilinx primitives to which the hierarchy resolves.
A UCF (User Constraints File) contains user-specified logical constraints.
Verification is the process of reading back the configuration data of a device and comparing it to the original design to ensure that all of the design was correctly received by the device.
An industry-standard HDL (IEEE Std 1364) originally developed by Cadence Design Systems, now maintained by OVI. Recognizable as a file with a .v extension.
Verilog is a commonly used Hardware Description Language (HDL) that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. It is IEEE standard 1364-1995.
VHSIC (VHSIC an acronym for Very High-Speed Integrated Circuits) Hardware Description Language. An industry-standard (IEEE 1076.1) HDL. Recognizable as a file with a .vhd or .vhdl extension.
VHDL is an acronym for VHSIC Hardware Description Language, which can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. It is IEEE standard 1076-1993.
A language that is capable of describing the concurrent and sequential behavior of a digital system with or without timing.
A wire is either 1) a net or 2) a signal.
Xilinx ABEL is a design entry package consisting of a Xilinx-specific version of the ABEL design entry software and a series of translation programs. It uses Boolean equations, truth tables, and state machines to create modules and full designs for CPLDs and modules for FPGAs.
In Foundation 1.4, this compiler synthesizes and generates EDIF 2 0 0 from Metamor VHDL code or state machine designs. It has been replaced by the Synopsys FPGA Express compiler for Foundation Series F1.5.