Design Description

Throughout this tutorial, the design is referred to as Watch.

The design used in this tutorial is a hierarchical, schematic-based design, meaning that the top-level design file is a schematic sheet which refers to several other lower-level macros. The lower-level macros are a variety of different types of modules including schematic-based modules, LogiBLOX modules, state machine modules, and HDL modules.

The design begins as an unfinished design. Throughout the tutorial, you will complete the design by creating some of the modules, and by completing some others from existing files. After the design is complete, you will simulate it to verify the functionality.

Watch is a simple runner's stopwatch. The completed schematic is shown in the following figure.

Figure 4.2 Completed Watch Schematic

There are two external inputs and three external outputs in the completed design. The system clock is an internally generated signal produced by OSC4, the internal oscillator in the XC4000 devices. The following list summarizes the inputs and outputs and their functions.

Inputs:

• STRTSTOP - Starts and stops the stopwatch. This is an active-low signal which acts like the start/stop button on a runner's stopwatch.
  
  
• RESET - Resets the stopwatch to 00.0 after it has been stopped.
  
  

Outputs:

• TENSOUT[6:0] - 7-bit bus which represents the Tens digit of the stopwatch value. This bus is in 7-segment display format to be viewable on the 7-segment LED display on the Xilinx demonstration board.
  
  
• ONESOUT[6:0] - similar to TENSOUT bus above, but represents the Ones digit of the stopwatch value.
  
  
• TENTHSOUT[9:0] - 10-bit bus which represents the Tenths digit of the stopwatch value. This bus is one-hot encoded.
  
  

The completed design consists of the following functional blocks. Most of these blocks do not appear yet on the schematic sheet in the tutorial project since they will be created during this tutorial.

Functional Blocks

• OSC4
  
  Xilinx Unified Library component which represents the XC4000 on-chip oscillator.
  
  
• STMACH_A or STMACH_V
  
  State Machine macro. This module uses the Foundation State Editor to enter and implement the state machine. One is an ABEL version; the other is a VHDL version.
  
  
• CNT60
  
  Schematic-based module which counts from 0 to 59, decimal. This macro has two 4-bit outputs, which represent the `ones' and `tens' digits of the decimal values, respectively.
  
  
• TENTHS
  
  LogiBLOX 10-bit, one-hot encoded counter. This macro outputs the `tenths' digit of the watch value as a 10-bit one-hot encoded value.
  
  
• HEX2LED
  
  HDL-based macro. This macro decodes the ones and tens digit values from hexadecimal to 7-segment display format to view on the FPGA Demonstration Board.
  
  
• OUTS1, OUTS2, OUTS3
  
  Schematic-based macros which define the external output pin assignments for TENSOUT, ONESOUT, and TENTHSOUT output buses.
  
  
• DEBUG_CKT
  
  Schematic-based macro containing the necessary logic to perform hardware debugging and readback using the Hardware Debugger.