목차
Introducing the Xilinx Spartan Series
Xilinx Spartan Families
Basic Architecture
Spartan Meets ASIC Requirements Low
Price
Total Cost Management
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Packages
UltraDenseTM 0.5? Process
UltraDenseTM Process
Advanced Process Technology eliminates
the “RAM compromise”
Xilinx Spartan Series
Spartan Series Footprint Compatibility
Xilinx Introduces First Fully Programmable
System Solution First FPGA Architecture
Designed for Intellectual Property
System Level Design Trend
Real Time Video Processor
Virtex Family Overview
Functional Block Diagram
Virtex Configurable Logic Block
Segmented Routing Interconnect
Block RAM
Virtex FPGA Performance
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XC5200 Family Overview
Flexible XC5200 Feature Set
XC5200 Architecture Overview
Abundant Routing with VersaBlockTM
XC5200 Configurable Logic Block
Abundant Routing Resources
VersaRingTM: High Utilization & Pin
Assignment Flexibility
XC5200 Family
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What is the CPLD
Functions of 5 Product Term are fastest
Pin Selection For CPLD
Why not EEPROM Technology?
ISP Market Growth
XC9500 CPLDs
XC9500 Key Features
XC9500 Architecture
Complete Interconnectivity with
FastCONNECT™
XC9500 FastCONNECT
FastFLASH Function Block
XC9500 Macrocell
Feedback Paths
What is Pin-Locking?
3 Keys to Pin-Locking
Keys to Pin-Locking
XC9500 Supports Design Changes with
Fixed Pinouts
CPLD Architecture Designed for Superior
Pin-Locking
Requirements to Support the Product Life
Cycle
XC9500 Other System Features
XC9500 Product Family
FLASH Process Technology Roadmap
Address Decoder Benchmark
Address Decoder Design Iteration
Address Decoder Pinlock Performance
Address Counter Benchmark
Address Counter Design Iteration
Address Counter Pinlock Performance
XC9500 Fits In Industry Standard JTAG
Chains
Advanced JTAG Download Software
Easy-To-Use XACTstep M1.4 for CPLDs
HardWireTM FpgASIC The Superior ASIC
Solution
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Design Flow for Implementation
Step 1: Invoke Design Manager
Step 2: Start a Project
Step 3: Specify Back Annotation
Step 3: Specify Back Annotation
Step 4: Implement the Design (1)
Step 4: Implement the Design (2)
Step 5. Check Results (1)
Step 5: Check Results (2)
Step 5: Check Results (3)
Step 5. Check Results (4)
Step 6: Configure the FPGA/CPLD |