This appendix contains glossary definitions of the terms used in this manual.
A basic element, for example, an individual flip-flop or LUT.
A group consisting of one or more logic functions.
Tristate buffer.
Configurable Logic Block.
A signal in a section of combinatorial logic that limits the speed of the logic. Synchronous elements begin and end a critical path, which may include an I/O pad.
A graphical representation of the MAP file in the Floorplanner Design Hierarchy window.
D-Latch or flip-flop.
An NCD file representing a previously placed and routed design, which is used in a subsequent place and route operation.
Hardware Description Language. The most common HDLs in use today are Verilog and VHDL. They describe designs in a technology- independent manner using a high level of abstraction.
An IOB is a collection or grouping of basic elements (BELs) that implement the input and output functions of an FPGA device.
The input/output logic of the device containing pin drivers, registers, and latches, and tristate control functions.
The input/output pads interface the design logic with the pins of the device.
Graphical representation of a logic resource, such as a flip-flop, buffer, or register.
Selected logic that is being moved from one location to another in the Floorplanner.
Each CLB column has four dedicated global vertical longlines, and each of these lines connects to a primary global net or to any secondary global net. These lines are very fast.
The process of assigning a design's logic elements to the specific FPGA physical elements that actually implement logic functions in a target device.
The area located at the top of the main window that provides access to the menus.
A logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.
The process of transforming a design to decrease its area or to increase its speed performance.
The physical bonding pad on an integrated circuit. All signals on a chip must enter and leave by way of a pad. Pads are connected to package pins in order for signals to enter or leave an integrated circuit package.
The process of assigning logic from your design to physical cell locations in the FPGA.
Lines that indicate connectivity between logic in the Floorplanner or Placement window.
Graphical representation of elements in the target FPGA Floorplan window, such as function generators, registers, tristate buffers in the CLB, and IOBs.
The process of assigning logical nets to physical wire segments in the FPGA that interconnect logic cells.
The utility that connects all appropriate pins to create the design's nets.
An electronic drawing representing a design in terms of primitive elements.
In the Floorplanner, the process of using the mouse to choose logic in either the Design Hierarchy window or the Floorplan window for placement, movement, or processing.
An area located at the bottom of a window that provides information about the commands that you are about to select or that are being processed.
A logic primitive with three possible output states.
A field located under the menu bar at the top of your window. It contains a series of icons (buttons) that you click on to execute some of the most commonly used commands. These buttons are an alternative to the menu commands.