TRACE

TRACE (Timing Reporter And Circuit Evaluator) provides static timing analysis of a design based on input timing constraints.

NOTE

On the command line, the TRACE command is entered as trce (without an “A”).

TRACE performs two major functions.

• Timing verification - the process of verifying that the design meets your timing constraints.
  
  
• Reporting - the process of enumerating input constraint violations and placing them into an accessible file. TRACE can be run on unplaced designs, completely placed and routed designs, or designs that are placed and routed to any degree of completion.
  
  

Figure 12.1 TRACE