NGD2EDIF

NGD2EDIF produces an EDIF 2 0 0 netlist in terms of the Xilinx primitive set, allowing you to simulate pre- and post-route designs.

NGD2EDIF can produce an EDIF file representing a design in any of these stages.

• An unmapped design - To translate an unmapped design, the input to NGD2EDIF is an NGD file - a logical description of your design. The output from NGD2EDIF is an EDIF file containing a functional description of the design without timing information.
  
  
• A mapped, unrouted design - To translate a mapped design that has not been placed and routed, the input to NGD2EDIF is an NGA file - an annotated logical description of your design - generated from a mapped physical design. The output from NGD2EDIF is an EDIF file containing a functional description of the design and timing information containing component delays but without routing delays.
  
  
• A routed design - To translate a design which has been placed and routed, the input to NGD2EDIF is an NGA file generated from a routed physical design. The output from NGD2EDIF is an EDIF file containing a functional description of the design and timing information containing both component and routing delays.
  
  

The design flow for NGD2EDIF is shown in the following figure.

Figure 16.1 NGD2EDIF Design Flow