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The Logical DRC Tests

The Logical DRC performs six types of checks.

The following sections describe these tests.

The Block Check

The block check verifies that each terminal symbol in the NGD hierarchy (that is, each symbol that is not resolved to any lower-level components) is an NGD primitive. A block check failure is treated as an error. As part of the block check, the DRC also checks user-defined properties on symbols and the values on the properties to make sure they are legal.

The Net Check

The net check determines the number of NGD primitive output pins (drivers), tristate pins (drivers) and input pins (loads) on each signal in the design. If a signal does not have at least one driver (or one tristate driver) and at least one load, a warning is generated. An error is generated if a signal has multiple non-tristate drivers or any combination of tristate and non-tristate drivers. As part of the net check, the DRC also checks user-defined properties on signals and the values on the properties to make sure they are legal.

The Pad Check

The pad check verifies that each signal connected to pad primitives obeys the following rules.

In addition to

The Clock Buffer Check

The clock buffer configuration check verifies that the output of each clock buffer primitive is connected to only inverter, flip-flop or latch primitive clock inputs, or other clock buffer inputs. Violations are treated as warnings.

The Name Check

The name check verifies the uniqueness of names on NGD objects as defined below. The tests, and the messages reported by a violation of the tests, are

The Primitive Pin Check

The primitive pin check verifies that certain pins on certain primitives are connected to signals in the design. The check tests these pins on these NGD primitive types.

NGD Primitive
Pins Checked
X_TRI
IN, OUT, and CTL
X_FF
IN, OUT, and CLK
X_LATCH
IN, OUT, and CLK
X_IPAD
PAD
X_OPAD
PAD
X_BPAD
PAD

If one of these pins is not connected to a signal, you receive a warning.

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