MAP maps a logical design to a Xilinx FPGA. The input to mapping is an NGD file, which contains a logical description of the design in terms of both the hierarchical components used to develop the design and the lower level Xilinx primitives, and any number of NMC (macro library) files, each of which contains the definition of a physical macro. MAP first performs a logical DRC (Design Rule Check) on the design in the NGD file. MAP then maps the logic to the components (logic cells, I/O cells, and other components) in the target Xilinx FPGA. The output design is an NCD (Native Circuit Description) file - a physical representation of the design mapped to the components in the Xilinx FPGA. The NCD file can then be placed and routed.
The flow through MAP is shown in the following figure. MAP can be invoked from the Design Manager/Flow Engine graphical interface or from the UNIX or DOS command line. The Design Manager/Flow Engine is described in the Design Manager/Flow Engine Reference/User Guide. This chapter describes running MAP from the UNIX or DOS command line.
Figure 6.1 MAP |  |
For Virtex, MAP does not support guide files.
