The MAP Report (MRP) File

The MAP report (MRP) file is an ASCII (text) file containing information about the MAP command run. Although detailed information varies depending upon the device to which you have mapped, the format of the file is the same regardless of the device used.

NOTE

The MRP file is formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the report uses a proportional font, the columns in the report do not line up correctly.

A sample MRP file is shown below. This is an abbreviated file - most MAP report files are considerably larger than the one shown below.

The report file is divided into a number of sections. Sections appear in the report file even if they are empty (that is, even if there are no messages that apply to them).

These are the sections in the MAP report file.

• Design Information - Shows your MAP command, line, the device to which the design has been mapped, and when the mapping was performed.
  
  
• Design Summary - Summarizes the mapper run, showing the number of errors and warnings, and how many of the resources in the target device are used by the mapped design.
  
  

• Table of Contents - Lists the remaining sections of the MAP report.
  
  

• Errors (Section 1) - Shows any errors generated as a result of the following.
  
  
  • Errors associated with the logical DRC tests performed at the beginning of the mapper run. These errors do not depend on the device to which you are mapping.
    
    
  • Errors the mapper discovers (for example, a pad is not connected to any logic, or a bidirectional pad is placed in the design but signals only pass in one direction through the pad). These errors may depend on the device to which you are mapping.
    
    
  • Errors associated with the physical DRC run on the mapped design.
    
    

• Warnings (Section 2) - Shows any warnings generated as a result of the following.
  
  
  • Warnings associated with the logical DRC tests performed at the beginning of the mapper run. These warnings do not depend on the device to which you are mapping.
    
    
  • Warnings the mapper discovers. These warnings may depend on the device to which you are mapping.
    
    
  • Warnings associated with the physical DRC run on the mapped design.
    
    

• Design Attributes (Section 3) - Shows any attributes (properties) specified when the design was created. Some of these attributes also appear as physical constraints in the physical constraints file (PCF) produced by the mapper run.
  
  
• Removed Logic Summary (Section 4) - Summarizes the number of blocks and signals removed from the design. The section reports on these kinds of removed logic.
  
  
  • Blocks trimmed - A “trimmed” block is a block removed because it is along a path that has no driver or no load. Trimming is recursive; that is, if Block A becomes unnecessary because logic to which it is connected has been trimmed, then Block A is also trimmed.
    
    
  • Blocks removed - A “removed” block is removed because it can be eliminated without changing the operation of the design. Removal is recursive; that is, if Block A becomes unnecessary because logic to which it is connected has been removed, then Block A is also removed.
    
    
  • Blocks optimized - An “optimized” block is a block removed because its output remains constant regardless of the state of the inputs (for example, an AND gate with one input tied to ground). Logic generating an input to this optimized block (and to no other blocks) is also removed, and appears in this section.
    
    
  • Signals removed - Signals that were removed because they were attached only to removed blocks.
    
    
  • Signals merged - A signal is merged when two signals are combined because a component separating them was removed.
    
    
• Removed Logic (Section 5) - Describes in detail all logic (design components and nets) removed from the input NGD file when the design was mapped. The preceding description of Section 4 defines the types of logic removed. More generally, logic may be removed because
  
  
  • A design uses only part of the logic in a library macro.
    
    
  • The design has been mapped even though it is not yet complete.
    
    
  • The mapper has optimized the design logic.
    
    
  • Unused logic has been created in error during schematic entry.
    
    

This section also indicates which nets were merged (that is, two nets were combined when a component separating them was removed).

In this section, if the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the line describing the subsequent removal is indented. This indentation is repeated as a chain of related logic is removed. To quickly locate the cause for the removal of a chain of logic, look above the entry in which you are interested and locate the top-level line, which is not indented.

• Added Logic (Section 6) - Describes any logic that was added to the design by the mapper. For example, logic is added when a design contains global reset buffers but the device to which you are mapping does not have global reset buffers. The mapper adds the necessary logic to perform the global reset function.
  
  
• Expanded Logic (Section 7) - If enabled, describes the mapping of logic that has been added to the database to resolve certain design blocks (for example, LogiBLOX modules).
  
  By default this section is empty, since the section may contain thousands of lines and the information is not needed by the majority of users. To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun MAP.
  
  
• Signal Cross Reference (Section 8) - If enabled, shows where nets in the logical design were mapped in the physical design. In this section, signals that are reported as “covered” have been mapped completely within a logic cell.
  
  By default this section is empty, since the section may contain thousands of lines and the information is not needed by the majority of users. To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun MAP.
  
  
• Symbol Cross Reference (Section 9) - If enabled, shows where symbols in the logical design were mapped in the physical design.
  
  By default this section is empty, since the section may contain thousands of lines and the information is not needed by the majority of users. To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun MAP.
  
  
• IOB Properties (Section 10) - Lists each IOB to which the user has supplied constraints along with the applicable constraints. The possible IOB properties are shown in the following table;
  
  the applicability of the properties and options varies from one architecture to another. The following table applies only to the XC4000X, Spartan and SpartanXL architectures.
  
  

  Table 6_2 IOB Properties

  Property	Meaning	Options
  SLEW	Output slew rate	SLOW or FAST
  PULLUP	Enable pull-up resistor	N/A
  PULLDOWN	Enable pull-down resistor	N/A
  FF/LATCH	Input flip-flop/latch data source	NODELAY, MEDDELAY, or SYNC
  SYNC	Fast capture latch data source	NODELAY or MEDDELAY
  DRIVE	Drive value on output pads	12 or 24 ma.

  
  
• 
  
  
  
  
• RPMs (Section 11) - Indicates each RPM (Relationally Placed Macro) used in the design, and the number of device components used to implement the RPM.
  
  
• Guide Report (Section 12) - If you have mapped using a guide file, shows the guide mode used (EXACT or LEVERAGE) and the percentage of objects that were successfully guided. (This section does not apply to Virtex.)
  
  

A sample MAP Report (MRP) file is shown below.

NOTE

The MAP Report is formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the report uses a proportional font, the columns in the report do not line up correctly.

             Xilinx Mapping Report File for Design “main_pcb”
              Copyright (c) 1995-1998 Xilinx, Inc.  All rights reserved.
    
    Design Information
    ------------------
    Command Line   : map -p xc4006epq160-4 main_pcb.ngd 
    Target Device  : x4006e
    Target Package : pq160
    Target Speed   : -4
    Mapper Version : xc4000e -- M1.5.15
    Mapped Date   : Tue Apr 28 09:41:41 1998 

   
Design Summary
    --------------
       Number of errors:        0
       Number of warnings:      0
       Number of CLBs:            248 out of   256   96%
          CLB Flip Flops:     311
          4 input LUTs:       394 (7 used as route-throughs)
          3 input LUTs:       138 (28 used as route-throughs)
          16X1 RAMs:           19
       Number of bonded IOBs:      95 out of   128   74%
          IOB Flops:            7
          IOB Latches:          5
       Number of clock IOB pads:    3 out of     8   37%
       Number of primary CLKs:      2 out of     4   50%
       Number of secondary CLKs:    2 out of     4   50%
       Number of RPM macros:        4
       Number of testdata:          1
       2 unrelated functions packed into 2 CLBs.
       (Less than 1% of the CLBs used are affected.) 

   
Total equivalent gate count for design: 6213
    Additional JTAG gate count for IOBs:    4608 

   
Table of Contents
    -----------------
    Section 1 - Errors
    Section 2 - Warnings
    Section 3 - Design Attributes
    Section 4 - Removed Logic Summary
    Section 5 - Removed Logic
    Section 6 - Added Logic
    Section 7 - Expanded Logic
    Section 8 - Signal Cross-Reference
    Section 9 - Symbol Cross-reference
    Section 10 - IOB Properties
    Section 11 - RPMs
    Section 12 - Guide Report
    Section 1 - Errors
    ------------------
    
    Section 2 - Warnings
    --------------------
    
    Section 3 - Design Attributes
    -----------------------------
     Attribute LOC
       “P117” for signal(s) D24 on symbol “D24.PAD”
       “P113” for signal(s) D25 on symbol “D25.PAD”
       “P106” for signal(s) D26 on symbol “D26.PAD”
               .
               .
               .
       “P152” for signal(s) INC_IDX_DBG on symbol “INC_IDX_DBG.PAD”
       “P129” for signal(s) XMT_PND_DBG on symbol “XMT_PND_DBG.PAD”
    
    Section 4 - Removed Logic Summary
    ---------------------------------
       6 block(s) removed
       6 block(s) optimized away
      11 signal(s) removed 

   
Section 5 - Removed Logic
    -------------------------
    The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections.  If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented.  This indentation will be repeated as a chain of related logic is removed. 

   To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge). 

   The signal "$2I194/O" is loadless and has been removed.
     Loadless block "$2I194/BUF" (X_BUF) removed.
    The signal "$2I206/O" is loadless and has been removed.
     Loadless block "$2I206/BUF" (X_BUF) removed.
    The signal "$2I226/O" is loadless and has been removed.
     Loadless block "$2I226/BUF" (X_BUF) removed.
    The signal "$2I236/O" is loadless and has been removed.
     Loadless block "$2I236/BUF" (X_BUF) removed.
    The signal "$2I286/O" is loadless and has been removed.
     Loadless block "$2I286/BUF" (X_BUF) removed.
    The signal "$3I565/O" is loadless and has been removed.
     Loadless block "$3I565/BUF" (X_BUF) removed.
    The signal "$2I194/GE" is sourceless and has been removed.
    The signal "$2I206/GE" is sourceless and has been removed.
    The signal "$2I226/GE" is sourceless and has been removed.
    The signal "$2I236/GE" is sourceless and has been removed.
    The signal "$2I286/GE" is sourceless and has been removed. 

   Optimized Block(s): 

   TYPE            BLOCK 

   X_ZERO          XNFPREP_GND_0.ZERO
    X_ZERO          DE/MX/GND.ZERO
    X_INV           $4I248/INTBUF
    X_INV           $4I528/INTBUF
    X_ZERO          GND.ZERO
    X_ONE           VCC.ONE 

   To enable printing of redundant blocks removed and signals merged, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun map.
    .
    
    Section 6 - Added Logic
    ----------------------- 

   
Section 7 - Expanded Logic
    --------------------------
    To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun map. 

   Section 8 - Signal Cross-Reference
    ----------------------------------
    To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun map. 

   Section 9 - Symbol Cross-Reference
    ----------------------------------
    To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUE and rerun map.
     

   Section 10 - IOB Properties
    ---------------------------
    "AMODE0" (IOB) : SLEW=SLOW
    "AMODE1" (IOB) : SLEW=SLOW
               .
               .
    "VSEN" (IOB) : SLEW=SLOW
    "VWBWEN" (IOB) : SLEW=SLOW PULLUP
    “XMT_PND_DBG” (IOB) : SLEW=SLOW
     

   Section 11 - RPMs
    -----------------
    $3I283/hset                              - 5 comps
    $6I223/hset                              - 4 comps
    DE/$1I385/hset                           - 5 comps
    DE/VR/$1I2/hset                          - 9 comps
     

   Section 12 - Guide Report
    -------------------------
    Guide not run on this design.