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X74_165S

8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
Macro
Macro
Macro
Macro
Macro
Macro
Macro
N/A

figures/x4180n.gif

X74_165S is an 8-bit shift register with serial-input (SI), parallel- inputs (H - A), parallel-outputs (QH - QA), and two control inputs - clock enable (CE) and active-Low shift/load enable (S_L). When S_L is Low, data on the H - A inputs is loaded into the corresponding QH - QA bits of the register on the Low-to-High clock (CK) transition. When CE and S_L are High, data on the SI input is loaded into the first bit of the register during the Low-to-High clock transition. During subsequent Low-to-High clock transitions, with CE and S_L High, the data is shifted to the next-highest bit position (shift right) as new data is loaded into QA (SI QA, QAQB, QBQC, and so forth). The register ignores clock transitions when CE is Low and S_L is High.

Registers can be cascaded by connecting the QH output of one stage to the SI input of the next stage and connecting clock, CE, and S_L inputs in parallel.

Inputs
Outputs
S_L
CE
SI
A - H
CK
QA
QB - QH
0
X
X
A - H

qa
qb - qh
1
0
X
X
X
No Chg
No Chg
1
1
SI
X

si
qA - qG
si = state of referenced input one setup time prior to active clock transition
qn = state of referenced output one setup time prior to active clock transition

Figure 11.26 X74_165S Implementation XC3000, XC4000, XC5200, XC9000, Spartans

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