CAPTURE_VIRTEX

Virtex Register State Capture for Bitstream Readback

CAPTURE_VIRTEX provides user control over when to capture register (flip-flop and latch) information for readback. Virtex provides the readback function through dedicated configuration port instructions, instead of with a READBACK component as in other FPGA architectures. The CAPTURE_VIRTEX symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available.

NOTE

Virtex only allows for capturing register (flip-flop and latch) states. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured.

An asserted High CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. The Low-to-High clock transition triggers the capture clock (CLK) which clocks out the readback data.

Two BitGen options control when capture can occur.

• When ONESHOT mode is set, only a single capture of registers for readback is allowed. After a trigger (transition on CLK while CAP is asserted), all register information is captured and no additional captures can occur until the readback operation is completed.
  
  
• When CONTINUOUS mode is set, data is captured after every trigger (transition on CLK while CAP is asserted).
  
  

For details on the Virtex readback function, refer to the Xilinx web site, (http://www.xilinx.com).