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FDE_1

D Flip-Flop with Negative-Edge Clock and Clock Enable

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Primitive

figures/x8362.gif

FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q). When clock enable is High, the data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition.

The flip-flop is asynchronously cleared, output Low, when power is applied. Virtex simulates power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_VIRTEX symbol.

Inputs
Outputs
CE
D
C
Q
0
X
X
No Chg
1
0

0
1
1

1

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