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FDPE_1

D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
N/A
Macro
Macro
Macro
N/A
Macro
Macro
Primitive

figures/x3852n.gif

FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the Q output High. Data on the D input is loaded into the flip-flop when PRE is Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored.

The flip-flop is asynchronously preset, output High, when global reset (GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The active level of the GR/GSR defaults to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.

Inputs
Outputs
PRE
CE
D
C
Q
1
X
X
X
1
0
0
X
X
No Chg
0
1
1

1
0
1
0

0

Figure 5.19 FDPE_1 Implementation XC4000, XC5200, Spartans

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