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FTCLE

Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro

figures/x3769n.gif

FTCLE is a toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When load enable input (L) is High and CLR is Low, clock enable (CE) is overridden and the data on data input (D) is loaded into the flip-flop during the Low-to-High clock (C) transition. When toggle enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High clock transition. When CE is Low, clock transitions are ignored.

The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs
Outputs
CLR
L
CE
T
D
C
Q
1
X
X
X
X
X
0
0
1
X
X
1

1
0
1
X
X
0

0
0
0
0
X
X
X
No Chg
0
0
1
0
X
X
No Chg
0
0
1
1
X

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Figure 5.53 FTCLE Implementation XC3000

Figure 5.54 FTCLE Implementation XC4000, XC5200, Spartans, Virtex

Figure 5.55 FTCLE Implementation XC9000

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