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FTP

Toggle Flip-Flop with Toggle Enable and Asynchronous Preset

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
N/A
Macro
Macro
Macro
Macro
Macro
Macro
Macro

figures/x3762n.gif

FTP is a toggle flip-flop with toggle enable and asynchronous preset. When the asynchronous preset (PRE) input is High, all other inputs are ignored and output Q is set High. When toggle-enable input (T) is High and PRE is Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition.

For FPGAs, the flip-flop is asynchronously preset to output High, when global reset (GR for XC5200) or global set/reset (GSR for XC4000, Spartans, Virtex) is active. The GR/GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or the STARTUP_VIRTEX symbol.

For CPLDs, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

Inputs
Outputs
PRE
T
C
Q
1
X
X
1
0
0
X
No Chg
0
1

Toggle

Figure 5.59 FTP Implementation XC4000, XC5200, Spartans, Virtex

Figure 5.60 FTP Implementation XC9000

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