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ILDI_1

Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)

XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
N/A
Macro
Macro
N/A
N/A
Macro
Macro
Macro

figures/x4618n.gif

ILDI_1 is a transparent data latch, which can hold transient data entering a chip. When the gate input (G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High G transition is stored in the latch.

The latch is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans) default to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.

For information on legal IFDI, IFDI_1, ILDI, and ILDI_1 combinations, refer to the “ILDI” section.

Inputs
Outputs
G
D
Q
0
1
1
0
0
0
1
X
d
d = state of input one setup time prior to High-to-Low gate transition

Figure 6.33 ILDI_1 Implementation XC4000, Spartans

Figure 6.34 ILDI_1 Implementation Virtex

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