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OFD, 4, 8, 16

Single- and Multiple-Output D Flip-Flops

Element
XC3000
XC4000E
XC4000X
XC5200
XC9000
Spartan
SpartanXL
Virtex
OFD
Primitive
Macro
Macro
Macro
Macro
Macro
Macro
Macro
OFD4,
OFD8,
OFD16
Macro
Macro
Macro
Macro
Macro
Macro
Macro
Macro

figures/x3778n.gif

figures/x3800n.gif

figures/x3812n.gif

figures/x3834n.gif

OFD, OFD4, OFD8, and OFD16 are single and multiple output D flip-flops except for XC5200 and XC9000. The flip-flops exist in an input/output block (IOB) for XC3000, XC4000, and Spartans. The outputs (for example, Q3 - Q0) are connected to OPADs or IOPADs. The data on the D inputs is loaded into the flip-flops during the Low-to-High clock (C) transition and appears on the Q outputs.

The flip-flops are asynchronously cleared with Low outputs when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs
Outputs
D
C
Q
D

dn
dn = state of referenced input one setup time prior to active clock transition

Figure 8.5 OFD Implementation XC4000, Spartans

Figure 8.6 OFD Implementation XC5200, Virtex

Figure 8.7 OFD Implementation XC9000

Figure 8.8 OFD8 Implementation XC3000, XC4000, XC5200, Spartans, Virtex

Figure 8.9 OFD8 Implementation XC9000

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