This appendix describes each of the components (cells) in the Xilinx XC00 synthesis library.
| Component Name | Component Description | Inferable |
|---|---|---|
| AND2-AND8 | AND Gates | X |
| BUF | Buffer | |
| BUFE | Tristate buffer (not available in XC9500XL designs) | X |
| BUFGSR | Global set/reset input buffer | |
| BUFGTS | Global tristate control input buffer (uses clock-enable p-term in XC9500XL) | |
| BUFG | Global clock (FastCLK) input buffer | |
| FDCE | D-Type Flip-Flop with Clear and Clock Enable | |
| FDCE_X | D-Type Flip-Flop with Clear and Clock Enable | X |
| FDCP | D-Type Flip-Flop with Asynchronous Clear and Preset | X |
| FDPE | D-Type Flip-Flop with Preset and Clock Enable (uses clock-enable p-term in XC9500XL) | |
| FDPE_X | D-Type Flip-Flop with Preset and Clock Enable | X |
| IBUF | Input Buffer | X |
| INV | Inverter | X |
| IOBUFE | Bi-Directional I/O Buffer | X |
| IOBUFE_F | Bidirectional I/O Buffer--fast slew rate | X |
| IOBUFE_S | Bidirectional I/O Buffer--slow slew rate | X |
| LD | D-Type Latch | X |
| OBUF | Output Buffer | X |
| OBUF_F | Output Buffer--fast slew rate | X |
| OBUF_S | Output Buffer--slow slew rate | X |
| OBUFE | Tristate Output Buffer | X |
| OBUFE_F | Tristate Output Buffer--fast slew rate | X |
| OBUFE_S | Tristate Output Buffer--slow slew rate | X |
| OR2-OR8 | OR Gates | X |
| XOR2-XOR8 | XOR Gates | X |
AND2 through AND8 are AND gates with 2 to 8 inputs.
The synthesizer uses these components when creating functions that require AND gates.
U1: AND2 port map (O=>out,I1=>in2,I0=>in1);
BUF is a non-inverting buffer.
The synthesizer does not use this component by inference.
U1: BUF port map (O=>out_port, I=>in_port);
BUFE is a non-inverting tristate buffer, with active-high enable. BUFE must not appear in XC9500XL designs.
The synthesizer uses these components when creating functions that require tristate buffers that drive internal signals.
U1: BUFE port map (O=>ts_out, I=>inp, E=>enable);
BUFG is an input buffer used to drive the Global clock signal ( GCK).
BUFG signals may be used for active-high or active-low (inverted) clocking, and for any other logic functions in the design.
The synthesizer does not use this component by inference.
U1: BUFG port map (O=>global_clk, I=>in_port);
BUFGSR is an input buffer used to drive the Global set/reset signal. BUFGSR signals can drive the CLR or PRE input of any flip-flop components, and any other logic functions in the design.
The synthesizer does not use this component by inference.
U1: BUFGSR port map (O=>global_sr, I=>in_port);
BUFGTS is a an input buffer used to drive the global tristate control signal (GTS). BUFGTS may be used either active-high or active-low (inverted) to drive the E input of OBUFE and IOBUFE type components, and any other logic functions in the design.
The synthesizer does not use this component by inference.
U1: BUFGTS port map (O=>global_oe, I=>in_port);
FDCE and FDCE_X are edge-triggered D-type flip-flops with clear and clock enable.
The synthesizer uses the FDCE_X component for all flip-flop functions requiring clock-enable, but not requiring asynchronous preset. The synthesizer does not use the FDCE component by inference.
U1: FDCE port map (Q=>out, D=>data, C=>clock, CLR=>async_clr, CE=>clk_enable);
FDCP is an edge-triggered D-type flip-flop with preset and clear.
The synthesizer uses this component for all functions that require D-type registers, but not clock-enable.
U1: FDCP port map (Q=>out, D=>data, C=>clock, CLR=>async_clr, PRE=>async_set);
FDPE and FDPE_X are edge-triggered D-type flip-flops with preset and enable.
The synthesizer uses the FDPE_X component for all flip-flop functions requiring clock-enable and asynchronous preset. The synthesizer does not use the FDPE component by inference.
U1: FDPE port map (Q=>out, D=>data, C=>clock, PRE=>async_preset, CE=>clk_enable);
IBUF is an input buffer.
The synthesizer uses these components to receive inputs from device pins.
U1: IBUF port map (O=>received_signal, I=>in_port);
INV is an inverter.
The synthesizer uses this component for signal inversion.
U1: INV port map (O=>not_in1, I=>in1);
IOBUFE is a non-inverting tristate I/O buffer with active-high enable. Output slew rate is controlled by CPLD fitter options (default is fast).
IOBUFE_F is an I/O buffer with fast output slew rate.
IOBUFE_S is an I/O buffer with slow output slew rate.
The synthesizer uses these components to transfer signals to and from bidirectional device I/O pins.
U1: IOBUFE port map (O=>received_signal, IO=>inout_port, I=>driving_signal, E=>output_enable);
LD is a D-type latch.
The synthesizer uses LD for all transparent latches. This component can be used by inference.
U1: LD port map (Q=>out, D=>data, G=>latch_enable);
OBUF is an output buffer. Output slew rate is controlled by CPLD fitter options (default is fast).
OBUF_F is an output buffer with fast output slew rate.
OBUF_S is an output buffer with slow output slew rate.
The synthesizer uses this component when creating external outputs to device pins.
U1: OBUF port map (O=>out_port, I=>driving_signal);
OBUFE is a tristate output buffer with active-high enable. Output slew rate is controlled by CPLD fitter options (default is fast).
OBUFE_F is a tristate output buffer with fast output slew rate.
OBUFE_S is a tristate output buffer with slow output slew rate.
The synthesizer uses this component when creating tristate external outputs which connect to device pins.
U1: OBUFE port map (O=>out_port, I=>driving_signal, E=enable);
OR2 through OR8 are OR gates with 2 to 8 inputs.
The synthesizer uses these components when creating functions that require OR gates.
U1: OR2 port map (O=>out, I1=>in2, I0=>in1);
XOR2 through XOR8 are XOR gates with 2 to 8 inputs.
The synthesizer uses these components when creating functions that require XOR gates.
U1: XOR2 port map (O=>out, I1=>in2, I0=>in1);
