After you have installed the Xilinx software you must configure the Synopsys Design Compiler and VSS simulator setup files to access the XC9000 libraries. This section shows you how to configure the setup files and verify that your setup is working properly.
The setup files are typically located in each design directory where Xilinx CPLD designs are processed.
You will find a sample setup file in $XILINX/synopsys/examples/template.synopsys_dc.setup_9k. You can copy this file to your design directory and change the file name to .synopsys_dc.setup.
For XC9000 designs, your Design Compiler setup file (.synopsys_dc.setup) must contain the following lines:
search path = { . \
Xilinx_path/synopsys/libraries/syn \
Synopsys_path/libraries/syn}
link_library = {xc9000.db}
target_library = {xc9000.db}
symbol_library = {xc9000.sdb}
compile_fix_multiple_port_nets = true
bus_naming_style = "%s<%d>"
bus_dimension_seperator_style = "><"
bus_inference_style = "%s<%d>"
edifout_netlist_only = true
edifout_write_properties_list= {INIT LOC PWR_MODE}
edifout_power_and_ground_representation = cell
edifout_no_array = true
edifout_ground_name=GND
edifout_ground_pin_name=GROUND
edifout_power_name=VCC
edifout_power_pin_name=VCC
Where Xilinx_path is the actual directory path where your Xilinx software is installed, and Synopsys_path is the actual path where your Synopsys software is installed.
You cannot use UNIX environment variables directly in the .synopsys_dc.setup file, but you may use the dc_shell variables, as shown in the template files.
For XC9000 designs, your VSS Simulator setup file, .synopsys_vss.setup, must contain the following lines:
SIMPRIM: $XILINX/synopsys/libraries/sim/lib/simprims
TIMEBASE = NS
TIME_RES_FACTOR = 0.1
You may use either the $XILINX environment variable or the actual path specification in the .synopsys_vss.setup file.
