When you first run the fitter before your pinout is committed, the software automatically selects pin locations for your I/O signals. Pin locations are selected which will give you the greatest flexibility to iterate your design without having to move any of the pins. Each time the fitter successfully implements your design, it creates a guide file (design_name.gyd), which contains all the resulting pinout information. After you commit your pinout, subsequent design iterations cause the guide file to be read by the fitter and your committed pinout will be preserved.
We strongly recommend that you allow the software to automatically generate your initial pinout. Attempting to select your own initial pin preferences reduces the ability of the fitter to implement your design successfully the first time. It further reduces the amount of logic changes you could make after locking your pinout.
If you have successfully fit a design into an CPLD device and you build a prototype containing the device, you will probably want to "lock" the pinout.
Lock Pins. The pinout saved in the selected revision (stored in design_name.gyd) is translated into pin location (LOC) constraints and written into a user constraint file (design_name.ucf). Implement). The previous pinout information will be read from the UCF file and used in the new design revision.If you want to tell the fitter to directly read the guide file (design_name.gyd) on the Unix command line, you should specify the "pinlock" option with the cpld command as follows:
cpld -pinlock design_name
The -pinlock parameter tells the fitter to read and obey the pinout from the guide file that was saved the last time the fitter completed.
The fitter will not move any of the pins contained in the guide file, even if it prevents the design from successfully mapping.
Whenever you specify a guide file (pin locking), the fitter automatically uses the same device and package as previously used, unless you override it with a different specific device and/or package.
The pin locations stored in the guide file are specified based on the top-level port names in your design. If you change the name of any of your ports, the corresponding pin will no longer be constrained to the location stored in the guide file.
When you iterate your design while your pins are locked, you are free to delete existing ports and/or add new ports. The fitter will automatically select the best locations for any new ports you add, after placing all the existing ports constrained by the guide file.
If you iterate your design and your pinout is not yet committed (you haven't built a prototype containing the device), you should not specify the pinlock option. Instead, allow the software to redefine the pinout of your modified design. This will continue to give you the greatest flexibility to iterate your design again after you commit your pinout.
You can assign explicit locations for pins in your design using the LOC attribute in dc_shell. Enter the following in dc_shell:
set_attribute port LOC pin_name -type string
where port is the name of the port being assigned.
For example, to place the "start" input port on pin 23:
set_attribute start LOC p23 -type string
For PC, PQ and VQ type packages, the pin_name takes the form "Pnn" where nn is a number. For example, for the PC84 package, the valid range for pin_name is P1 through P84. For grid array type packages (PG and BG), the pin_name takes the form "rc", where r is the row letter and c is the column number.
You can also specify pin locations interactively using the Constraints Editor tool invoked from the Design Manager.
When your design contains LOC attributes, you should specify the target device type in the Design Manager Part Selector menu or using the cpld command's -p parameter (see Target Device Selection in this Chapter). The LOC attributes are typically not compatible when retargeting a design between different package types, device types or device families.
The LOC attributes are unconditional in that the software will not attempt to relocate a pin if it cannot achieve the specified assignment. If you specify a set of LOC attributes that the fitter cannot satisfy, the fitter will terminate with an error.
The LOC attributes override the pin assignments in the guide file if you specify the pinlock option. This allows you to make explicit changes to your committed pinout. If you override the guide file using LOC attributes, the software will issue a warning.
If your objective is to preserve a previously created pinout, we recommend you use the pinlock feature instead of creating a set of LOC attributes with the existing pin locations. The guide file saved from the previous design implementation contains additional information to help the fitter to successfully fit your modified design.
If you used LOC attributes when compiling your netlist but you want to temporarily allow the fitter automatically assign all I/O pins, place a check in the Ignore Design Assignments box in the Basic tab of the Implementation Options template:
ImplementTo temporarily allow the fitter automatically assign all I/O pins when using the Unix command line, you can specify the -ignoreloc parameter on the cpld command:
cpld -ignoreloc design_name
The -ignoreloc option allows you to temporarily ignore all the LOC attributes in your netlist. This is useful if you want to test how your design fits a different target device without re-compiling your design.
Prohibit I/O Locations allows you to reserve device pins for later use, or simply prevent them from being used at all. For instance, if you anticipate design changes in the future and want to set traces on your printed circuit board now, you can use this feature to prevent the fitter from using pins associated with those traces. Then, when you decide to use the traces, you can use the LOC attribute to assign those pins to new input/output buffers you place in your design.
In the Constraints Editor, Prohibit I/O Locations prevents all selected I/O pins from being used by the design. This dialog can be entered using a dialog box provided in the Ports tab.
You can apply the LOC attribute to as many ports in your design as you like. However, each pin assignment further constrains the software making it more difficult for the fitter to automatically allocate logic and I/O resources for the remaining I/O signals in your design.
When you manually assign output and I/O pins, you force the software to place associated logic functions into specific macrocells and specific function blocks. If the associated logic does not exceed the available function block resources (macrocells, product terms, and FastCONNECT inputs), the logic is mapped into the macrocell and the design will route in the FastCONNECT.
It is usually best to allow the fitter to automatically assign most or all of the pins based on the most efficient placement of logic in the device. The fitter automatically establishes a pinout which best allows for future design iterations without pin relocation. Any manual pin assignments you make in your design may not allow as much tolerance for changes in the logic associated with those pins, and in the logic physically mapped to nearby locations in the device.
If you are assigning pin locations to ports used as clocks, asynchronous set/reset, or output enable in your design, you should assign them to the GCK, GSR and GTS pins on the device if you want to take advantage of these global resources. The fitter will still automatically assign other clock, set/reset and output enable inputs to remaining GCK, GSR and GTS pins if available.
