Recommended CPLD Simulation Strategy

Because of the flexibility of the simulation environment, there are many ways in which you can verify your design. The following steps, which are explained in subsequent sections, show you one recommended flow for CPLD simulation.

1. Specify the initial states of your registers. If you use attributes to control the initial states of the registers in your actual design implementation, you should also re-specify those initial states in your source VHDL design file for functional simulation.
   
   
2. Create a test bench file. By following the guidelines described in this chapter, the same test bench can be used for both functional and timing simulation without modification.
   
   
3. Perform functional simulation. This allows you to debug the logic in your source design before implementing a CPLD.
   
   
4. Implement the design in a CPLD. This provides the necessary physical resource information necessary for timing simulation.
   
   
5. Prepare the timing model. The ngd2vhdl command or Simulation Output options in the Design Manager prepare the VITAL (the ngd2ver command prepares a Verilog HDL timing model) timing model of your design for simulation.
   
   
6. Perform timing simulation. By re-using the functional simulation test bench file, you can easily compare results and prevent errors that can be caused by accidental differences between separate test bench files.
   
   

All of these preparation and simulation steps are demonstrated in the design example shown in the "Getting Started with Xilinx CPLDs" chapter.